Adding key timeout output port to allow core to inform the top level wrapper that timeout has occured. Added functionality to zeroise API key registers when timout has happened. Updated all auto_zeroise test cases to check that API key registers are properly zeroised.

2 files changed, 8 insertions, 4 deletions

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index d6a2b5e..b41f476 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -166,6 +166,7 @@ module keywrap #(parameter ADDR_BITS = 13)
   wire [63 : 0]  core_a_init;
   wire [63 : 0]  core_a_result;
   wire [31 : 0]  core_api_rd_data;
+  wire           core_timeout;
 
 
   //----------------------------------------------------------------
@@ -198,9 +199,10 @@ module keywrap #(parameter ADDR_BITS = 13)
                     .valid(core_valid),
                     .loaded(core_loaded),
 
-                    .timeout(timeout_reg),
+                    .timeout_delay(timeout_reg),
                     .ping(ping_reg),
                     .zeroise(zeroise_reg),
+                    .timeout(core_timeout),
 
                     .rlen(rlen_reg),
 
@@ -270,7 +272,7 @@ module keywrap #(parameter ADDR_BITS = 13)
           if (a1_we)
             a1_reg <= write_data;
 
-          if (zeroise_reg)
+          if (zeroise_reg || core_timeout)
             begin
               for (i = 0 ; i < 8 ; i = i + 1)
                 key_reg[i] <= 32'h0;
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index adb3099..5a6f953 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -53,9 +53,10 @@ module keywrap_core #(parameter MEM_BITS = 11)
                      output wire                      valid,
                      output wire                      loaded,
 
-                     input wire [31 : 0]              timeout,
+                     input wire [31 : 0]              timeout_delay,
                      input wire                       ping,
                      input wire                       zeroise,
+                     output wire                      timeout,
 
                      input wire [(MEM_BITS - 2) : 0]  rlen,
 
@@ -205,6 +206,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
   assign ready    = ready_reg;
   assign valid    = valid_reg;
   assign loaded   = key_loaded_reg;
+  assign timeout  = key_timeout;
 
 
   //----------------------------------------------------------------
@@ -396,7 +398,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
 
       if (key_timeout_ctr_set || ping)
         begin
-          key_timeout_ctr_new = timeout;
+          key_timeout_ctr_new = timeout_delay;
           key_timeout_ctr_we  = 1'h1;
         end
       else if (key_timeout_ctr_dec)