Interface debugging.

2 files changed, 34 insertions, 24 deletions

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 6020731..9b80008 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -100,6 +100,12 @@ module keywrap(
   reg keylen_reg;
   reg config_we;
 
+  reg api_cs_reg;
+  reg api_cs_new;
+
+  reg api_we_reg;
+  reg api_we_new;
+
   reg [12 : 0] rlen_reg;
   reg [12 : 0] rlen_we;
 
@@ -117,9 +123,8 @@ module keywrap(
   reg            tmp_error;
 
   wire           core_ready;
+  wire           core_valid;
   wire [255 : 0] core_key;
-  wire           core_api_cs;
-  wire           core_api_we;
   wire [31 : 0]  core_api_rd_data;
 
 
@@ -141,18 +146,19 @@ module keywrap(
                     .reset_n(reset_n),
 
                     .init(init_reg),
-                    .start(next_reg),
+                    .next(next_reg),
                     .encdec(encdec_reg),
 
                     .ready(core_ready),
+                    .valid(core_valid),
 
-                    .rlen(rlen_reg)
+                    .rlen(rlen_reg),
 
                     .key(core_key),
                     .keylen(keylen_reg),
 
-                    .api_cs(core_api_cs),
-                    .api_we(core_api_we),
+                    .api_cs(api_cs_reg),
+                    .api_we(api_we_reg),
                     .api_wr_data(write_data),
                     .api_rd_data(core_api_rd_data)
                    );
@@ -177,6 +183,8 @@ module keywrap(
           rlen_reg   <= 13'h0;
           valid_reg  <= 1'h0;
           ready_reg  <= 1'h0;
+          api_cs_reg <= 1'h0;
+          api_we_reg <= 1'h0;
         end
       else
         begin
@@ -184,6 +192,8 @@ module keywrap(
           valid_reg  <= core_valid;
           init_reg   <= init_new;
           next_reg   <= next_new;
+          api_cs_reg <= api_cs_new;
+          api_we_reg <= api_we_new;
 
           if (config_we)
             begin
@@ -207,16 +217,15 @@ module keywrap(
   //----------------------------------------------------------------
   always @*
     begin : api
-      init_new         = 1'h0;
-      next_new         = 1'h0;
-      config_we        = 1'h0;
-      rlen_we          = 1'h0;
-      key_we           = 1'h0;
-      core_api_cs      = 1'h0;
-      core_api_we      = 1'h0;
-      core_api_rd_data = 32'h0;
-      tmp_read_data    = 32'h0;
-      tmp_error        = 1'h0;
+      init_new      = 1'h0;
+      next_new      = 1'h0;
+      config_we     = 1'h0;
+      rlen_we       = 1'h0;
+      key_we        = 1'h0;
+      api_cs_new    = 1'h0;
+      api_we_new    = 1'h0;
+      tmp_read_data = 32'h0;
+      tmp_error     = 1'h0;
 
       if (cs)
         begin
@@ -239,8 +248,8 @@ module keywrap(
 
               if (address == ADDR_WRITE_DATA)
                 begin
-                  core_api_cs = 1'h1;
-                  core_api_we = 1'h1;
+                  api_cs_new = 1'h1;
+                  api_we_new = 1'h1;
                 end
             end // if (we)
 
@@ -253,16 +262,16 @@ module keywrap(
                 ADDR_CTRL:    tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
                 ADDR_STATUS:  tmp_read_data = {30'h0, valid_reg, ready_reg};
 
-              if (address == ADDR_READ_DATA)
-                begin
-                  core_api_cs   = 1'h1;
-                  tmp_read_data = core_api_rd_data;
-                end
-
                 default:
                   begin
                   end
               endcase // case (address)
+
+              if (address == ADDR_READ_DATA)
+                begin
+                  api_cs_new = 1'h1;
+                  tmp_read_data   = core_api_rd_data;
+                end
             end
         end
     end // addr_decoder
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 9695b0b..8d0e455 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -49,6 +49,7 @@ module keywrap_core (
                      input wire           encdec,
 
                      output wire          ready,
+                     output wire          valid,
 
                      input wire [12 : 0]  rlen,