Adding delay cycle to API regs to match the latency for accessing the blockRAM. Added test case that checks access to the API regs.

1 files changed, 51 insertions, 42 deletions

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 58d40c0..885578b 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -92,7 +92,7 @@ module keywrap(
 
   localparam CORE_NAME0       = 32'h6b657920; // "key "
   localparam CORE_NAME1       = 32'h77726170; // "wrap"
-  localparam CORE_VERSION     = 32'h302e3730; // "0.70"
+  localparam CORE_VERSION     = 32'h302e3731; // "0.71"
 
 
   //----------------------------------------------------------------
@@ -123,6 +123,9 @@ module keywrap(
   reg [31 : 0] key_reg [0 : 7];
   reg          key_we;
 
+  reg [31 : 0] api_rd_delay_reg;
+  reg [31 : 0] api_rd_delay_new;
+
   reg valid_reg;
   reg ready_reg;
 
@@ -198,23 +201,25 @@ module keywrap(
           for (i = 0 ; i < 8 ; i = i + 1)
             key_reg[i] <= 32'h0;
 
-          init_reg   <= 1'h0;
-          next_reg   <= 1'h0;
-          encdec_reg <= 1'h0;
-          keylen_reg <= 1'h0;
-          r_bank_reg <= 7'h0;
-          rlen_reg   <= 13'h0;
-          valid_reg  <= 1'h0;
-          ready_reg  <= 1'h0;
-          a0_reg     <= 32'h0;
-          a1_reg     <= 32'h0;
+          init_reg         <= 1'h0;
+          next_reg         <= 1'h0;
+          encdec_reg       <= 1'h0;
+          keylen_reg       <= 1'h0;
+          r_bank_reg       <= 7'h0;
+          rlen_reg         <= 13'h0;
+          valid_reg        <= 1'h0;
+          ready_reg        <= 1'h0;
+          a0_reg           <= 32'h0;
+          a1_reg           <= 32'h0;
+          api_rd_delay_reg <= 32'h0;
         end
       else
         begin
-          ready_reg  <= core_ready;
-          valid_reg  <= core_valid;
-          init_reg   <= init_new;
-          next_reg   <= next_new;
+          ready_reg        <= core_ready;
+          valid_reg        <= core_valid;
+          init_reg         <= init_new;
+          next_reg         <= next_new;
+          api_rd_delay_reg <= api_rd_delay_new;
 
           if (config_we)
             begin
@@ -247,17 +252,24 @@ module keywrap(
   //----------------------------------------------------------------
   always @*
     begin : api
-      init_new      = 1'h0;
-      next_new      = 1'h0;
-      config_we     = 1'h0;
-      rlen_we       = 1'h0;
-      r_bank_we     = 1'h0;
-      key_we        = 1'h0;
-      core_api_we   = 1'h0;
-      a0_we         = 1'h0;
-      a1_we         = 1'h0;
-      tmp_read_data = 32'h0;
-      tmp_error     = 1'h0;
+      init_new         = 1'h0;
+      next_new         = 1'h0;
+      config_we        = 1'h0;
+      rlen_we          = 1'h0;
+      r_bank_we        = 1'h0;
+      key_we           = 1'h0;
+      core_api_we      = 1'h0;
+      a0_we            = 1'h0;
+      a1_we            = 1'h0;
+      tmp_read_data    = 32'h0;
+      tmp_error        = 1'h0;
+      api_rd_delay_new = 32'h0;
+
+      // api_mux
+      if (address[7])
+        tmp_read_data = core_api_rd_data;
+      else
+        tmp_read_data = api_rd_delay_reg;
 
       if (cs)
         begin
@@ -290,41 +302,38 @@ module keywrap(
               if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
                 core_api_we = 1'h1;
             end // if (we)
-
           else
             begin
+              // Read access
               if (address == ADDR_NAME0)
-                tmp_read_data = CORE_NAME0;
+                api_rd_delay_new = CORE_NAME0;
 
               if (address == ADDR_NAME1)
-                tmp_read_data = CORE_NAME1;
+                api_rd_delay_new = CORE_NAME1;
 
               if (address == ADDR_VERSION)
-                tmp_read_data = CORE_VERSION;
+                api_rd_delay_new = CORE_VERSION;
 
               if (address == ADDR_CTRL)
-                tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
+                api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
 
               if (address == ADDR_STATUS)
-                tmp_read_data = {30'h0, valid_reg, ready_reg};
+                api_rd_delay_new = {30'h0, valid_reg, ready_reg};
 
               if (address == ADDR_RLEN)
-                tmp_read_data = {19'h0, rlen_reg};
+                api_rd_delay_new = {19'h0, rlen_reg};
 
               if (address == ADDR_R_BANK)
-                tmp_read_data = {25'h0, r_bank_reg};
+                api_rd_delay_new = {25'h0, r_bank_reg};
 
               if (address == ADDR_A0)
-                tmp_read_data = core_a_result[63 : 32];
+                api_rd_delay_new = core_a_result[63 : 32];
 
               if (address == ADDR_A1)
-                tmp_read_data = core_a_result[31 : 0];
-
-              if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
-                tmp_read_data = core_api_rd_data;
-                end
-            end
-    end // addr_decoder
+                api_rd_delay_new = core_a_result[31 : 0];
+            end // else: !if(we)
+        end // if (cs)
+    end // block: api
 endmodule // keywrap
 
 //======================================================================