diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-07-05 10:24:58 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-07-05 10:24:58 +0200 |
| commit | 274862150052b4e62de20a52519a517ef1f9a3ff (patch) | |
| tree | 7e28400fb1f21888e3ffb8ec497692bf0b690497 /src/rtl | |
| parent | 6b15816bff4c0c3ab22bf6d8185da48a263f7727 (diff) | |
Debugged keywrap processing including A update. All AES operations works correctly. Now we just need to stop processing whe we should.
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/keywrap_core.v | 12 | ||||
| -rw-r--r-- | src/rtl/keywrap_mem.v | 4 |
2 files changed, 9 insertions, 7 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 07a079b..bb7cc09 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -134,6 +134,7 @@ module keywrap_core ( reg update_state; reg core_we; + reg [12 : 0] core_addr; reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; @@ -150,7 +151,7 @@ module keywrap_core ( .api_rd_data(api_rd_data), .core_we(core_we), - .core_addr(block_ctr_reg), + .core_addr(core_addr), .core_wr_data(core_wr_data), .core_rd_data(core_rd_data) ); @@ -230,8 +231,9 @@ module keywrap_core ( begin : keywrap_dp reg [63 : 0] xor_val; - a_new = 64'h0; - a_we = 1'h0; + a_new = 64'h0; + a_we = 1'h0; + core_addr = block_ctr_reg - 1'h1; core_we = 1'h0; aes_block = {a_reg, core_rd_data}; @@ -258,12 +260,12 @@ module keywrap_core ( //---------------------------------------------------------------- always @* begin : block_ctr - block_ctr_new = 13'h0; + block_ctr_new = 13'h1; block_ctr_we = 1'h0; if (block_ctr_rst) begin - block_ctr_new = 13'h0; + block_ctr_new = 13'h1; block_ctr_we = 1'h1; end diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v index dc08bab..6a70ebe 100644 --- a/src/rtl/keywrap_mem.v +++ b/src/rtl/keywrap_mem.v @@ -138,10 +138,10 @@ module keywrap_mem ( if (core_we) begin - mem0_data = core_wr_data[31 : 0]; + mem0_data = core_wr_data[63 : 32]; mem0_addr = core_addr; mem0_we = 1'h1; - mem1_data = core_wr_data[63 : 32]; + mem1_data = core_wr_data[31 : 0]; mem1_addr = core_addr; mem1_we = 1'h1; end |