Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.

1 files changed, 32 insertions, 26 deletions

diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index 6a70ebe..9d8e63d 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -37,33 +37,39 @@
 //
 //======================================================================
 
-module keywrap_mem (
-                    input wire           clk,
-
-                    input wire           api_we,
-                    input wire [13 : 0]  api_addr,
-                    input wire [31 : 0]  api_wr_data,
-                    output wire [31 : 0] api_rd_data,
-
-                    input wire           core_we,
-                    input wire [12 : 0]  core_addr,
-                    input wire [63 : 0]  core_wr_data,
-                    output wire [63 : 0] core_rd_data
+module keywrap_mem #(parameter API_ADDR_BITS = 11)
+                   (
+                    input wire                            clk,
+
+                    input wire                            api_we,
+                    input wire [(API_ADDR_BITS - 1) : 0]  api_addr,
+                    input wire [31 : 0]                   api_wr_data,
+                    output wire [31 : 0]                  api_rd_data,
+
+                    input wire                            core_we,
+                    input wire [(API_ADDR_BITS - 2) : 0]  core_addr,
+                    input wire [63 : 0]                   core_wr_data,
+                    output wire [63 : 0]                  core_rd_data
                    );
 
+  //----------------------------------------------------------------
+  // Parameters.
+  //----------------------------------------------------------------
+  localparam NUM_BANK_WORDS = 2 ** (API_ADDR_BITS - 1);
+
 
   //----------------------------------------------------------------
   // Registers and memories including control signals.
   //----------------------------------------------------------------
-  reg [31 : 0] mem0 [0 : 8191];
-  reg [31 : 0] mem0_data;
-  reg [12 : 0] mem0_addr;
-  reg          mem0_we;
+  reg [31 : 0]                  mem0 [0 : (NUM_BANK_WORDS - 1)];
+  reg [31 : 0]                  mem0_data;
+  reg [(API_ADDR_BITS - 2) : 0] mem0_addr;
+  reg                           mem0_we;
 
-  reg [31 : 0] mem1 [0 : 8191];
-  reg [31 : 0] mem1_data;
-  reg [12 : 0] mem1_addr;
-  reg          mem1_we;
+  reg [31 : 0]                  mem1 [0 : (NUM_BANK_WORDS - 1)];
+  reg [31 : 0]                  mem1_data;
+  reg [(API_ADDR_BITS - 2) : 0] mem1_addr;
+  reg                           mem1_we;
 
 
   //----------------------------------------------------------------
@@ -90,7 +96,7 @@ module keywrap_mem (
   always @(posedge clk)
     begin : mem0_access
       core_rd_data0   <= mem0[core_addr];
-      api_rd_data0    <= mem0[api_addr[13 : 1]];
+      api_rd_data0    <= mem0[api_addr[(API_ADDR_BITS - 1) : 1]];
 
       if (mem0_we)
         mem0[mem0_addr] <= mem0_data;
@@ -103,7 +109,7 @@ module keywrap_mem (
   always @(posedge clk)
     begin : mem1_access
       core_rd_data1   <= mem1[core_addr];
-      api_rd_data1    <= mem1[api_addr[13 : 1]];
+      api_rd_data1    <= mem1[api_addr[(API_ADDR_BITS - 1) : 1]];
 
       if (mem1_we)
         mem1[mem1_addr] <= mem1_data;
@@ -130,10 +136,10 @@ module keywrap_mem (
   always @*
     begin : write_mux
       mem0_data = 32'h0;
-      mem0_addr = 13'h0;
+      mem0_addr = {(API_ADDR_BITS - 1){1'h0}};
       mem0_we   = 1'h0;
       mem1_data = 32'h0;
-      mem1_addr = 13'h0;
+      mem1_addr = {(API_ADDR_BITS - 1){1'h0}};
       mem1_we   = 1'h0;
 
       if (core_we)
@@ -148,9 +154,9 @@ module keywrap_mem (
 
       else if (api_we)
         begin
-          mem0_addr = api_addr[13 : 1];
+          mem0_addr = api_addr[(API_ADDR_BITS - 1) : 1];
           mem0_data = api_wr_data;
-          mem1_addr = api_addr[13 : 1];
+          mem1_addr = api_addr[(API_ADDR_BITS - 1) : 1];
           mem1_data = api_wr_data;
 
           if (api_addr[0])