(1) Added initial version of keywrap_core which will implement the actual wrapping using aes_core and the keywrap_mem. (2) Minor cleanup to the keywrap_mem code.

1 files changed, 26 insertions, 24 deletions

diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index 8ddb465..e54798a 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -37,46 +37,48 @@
 //
 //======================================================================
 
-module keywrap_mem
+module keywrap_mem (
+                    input wire           clk,
+                    input wire           reset_n,
 
-  (
-   input wire           clk,
-   input wire           reset_n,
+                    input wire           api_we,
+                    input wire [13 : 0]  api_addr,
+                    input wire [31 : 0]  api_wr_data,
+                    output wire [31 : 0] api_rd_data,
 
-   input wire           api_we,
-   input wire [13 : 0]  api_addr,
-   input wire [31 : 0]  api_wr_data,
-   output wire [31 : 0] api_rd_data,
-
-   input wire           core_we,
-   input wire [12 : 0]  core_addr,
-   input wire [63 : 0]  core_wr_data,
-   output wire [63 : 0] core_rd_data
-  );
+                    input wire           core_we,
+                    input wire [12 : 0]  core_addr,
+                    input wire [63 : 0]  core_wr_data,
+                    output wire [63 : 0] core_rd_data
+                   );
 
 
   //----------------------------------------------------------------
-  // Registers and memories including conntrol signals.
+  // Registers and memories including control signals.
   //----------------------------------------------------------------
-  reg [31 : 0] tmp_api_rd_data0;
-  reg [31 : 0] tmp_api_rd_data1;
-  reg [31 : 0] muxed_tmp_api_rd_data;
-
-  reg [31 : 0] tmp_core_rd_data0;
-  reg [31 : 0] tmp_core_rd_data1;
-
   reg [31 : 0] mem0 [0 : 8191];
   reg [31 : 0] mem0_data;
-  reg  [12 : 0] mem0_addr;
+  reg [12 : 0] mem0_addr;
   reg          mem0_we;
 
   reg [31 : 0] mem1 [0 : 8191];
   reg [31 : 0] mem1_data;
-  reg  [12 : 0] mem1_addr;
+  reg [12 : 0] mem1_addr;
   reg          mem1_we;
 
 
   //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  reg [31 : 0] tmp_api_rd_data0;
+  reg [31 : 0] tmp_api_rd_data1;
+  reg [31 : 0] muxed_tmp_api_rd_data;
+
+  reg [31 : 0] tmp_core_rd_data0;
+  reg [31 : 0] tmp_core_rd_data1;
+
+
+  //----------------------------------------------------------------
   // Assignments for ports.
   //----------------------------------------------------------------
   assign api_rd_data = muxed_tmp_api_rd_data;