Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.

1 files changed, 34 insertions, 32 deletions

diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 8d8f101..d1e63b0 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -40,29 +40,30 @@
 //
 //======================================================================
 
-module keywrap_core (
-                     input wire           clk,
-                     input wire           reset_n,
+module keywrap_core #(parameter MEM_BITS = 11)
+                    (
+                     input wire                       clk,
+                     input wire                       reset_n,
 
-                     input wire           init,
-                     input wire           next,
-                     input wire           encdec,
+                     input wire                       init,
+                     input wire                       next,
+                     input wire                       encdec,
 
-                     output wire          ready,
-                     output wire          valid,
+                     output wire                      ready,
+                     output wire                      valid,
 
-                     input wire [12 : 0]  rlen,
+                     input wire [(MEM_BITS - 2) : 0]  rlen,
 
-                     input wire [255 : 0] key,
-                     input wire           keylen,
+                     input wire [255 : 0]             key,
+                     input wire                       keylen,
 
-                     input wire  [63 : 0] a_init,
-                     output wire [63 : 0] a_result,
+                     input wire  [63 : 0]             a_init,
+                     output wire [63 : 0]             a_result,
 
-                     input wire           api_we,
-                     input wire  [13 : 0] api_addr,
-                     input wire [31 : 0]  api_wr_data,
-                     output wire [31 : 0] api_rd_data
+                     input wire                       api_we,
+                     input wire  [(MEM_BITS - 1) : 0] api_addr,
+                     input wire [31 : 0]              api_wr_data,
+                     output wire [31 : 0]             api_rd_data
                     );
 
 
@@ -100,13 +101,13 @@ module keywrap_core (
   reg          valid_new;
   reg          valid_we;
 
-  reg [12 : 0] block_ctr_reg;
-  reg [12 : 0] block_ctr_new;
-  reg          block_ctr_we;
-  reg          block_ctr_dec;
-  reg          block_ctr_inc;
-  reg          block_ctr_rst;
-  reg          block_ctr_set;
+  reg [(MEM_BITS - 2) : 0] block_ctr_reg;
+  reg [(MEM_BITS - 2) : 0] block_ctr_new;
+  reg                      block_ctr_we;
+  reg                      block_ctr_dec;
+  reg                      block_ctr_inc;
+  reg                      block_ctr_rst;
+  reg                      block_ctr_set;
 
   reg [2 : 0]  iteration_ctr_reg;
   reg [2 : 0]  iteration_ctr_new;
@@ -133,16 +134,17 @@ module keywrap_core (
 
   reg            update_state;
 
-  reg            core_we;
-  reg [12 : 0]   core_addr;
-  reg [63 : 0]   core_wr_data;
-  wire [63 : 0]  core_rd_data;
+  reg                      core_we;
+  reg [(MEM_BITS - 2) : 0] core_addr;
+  reg [63 : 0]             core_wr_data;
+  wire [63 : 0]            core_rd_data;
 
 
   //----------------------------------------------------------------
   // Instantiations.
   //----------------------------------------------------------------
-  keywrap_mem mem(
+  keywrap_mem #(.API_ADDR_BITS(MEM_BITS))
+              mem(
                   .clk(clk),
 
                   .api_we(api_we),
@@ -194,7 +196,7 @@ module keywrap_core (
           a_reg                 <= 64'h0;
           ready_reg             <= 1'h1;
           valid_reg             <= 1'h1;
-          block_ctr_reg         <= 13'h0;
+          block_ctr_reg         <= {(MEM_BITS - 1){1'h0}};
           iteration_ctr_reg     <= 3'h0;
           keywrap_core_ctrl_reg <= CTRL_IDLE;
        end
@@ -269,12 +271,12 @@ module keywrap_core (
   //----------------------------------------------------------------
   always @*
     begin : block_ctr
-      block_ctr_new = 13'h0;
+      block_ctr_new = {(MEM_BITS - 1){1'h0}};
       block_ctr_we  = 1'h0;
 
       if (block_ctr_rst)
         begin
-          block_ctr_new = 13'h0;
+          block_ctr_new = {(MEM_BITS - 1){1'h0}};
           block_ctr_we  = 1'h1;
         end