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authorJoachim StroĢˆmbergson <joachim@secworks.se>2018-09-14 15:01:59 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2018-09-14 15:01:59 +0200
commitfa3ebe9f36310af061aba162713676b548555017 (patch)
tree9f0061951f9c0b8f3aface68c5129d432c647828 /src/rtl/keywrap_core.v
parent6cfcc1ec5bc0e2c944ec66bd62d58740d2b8823d (diff)
Adding support for automatic A-value and RLEN calculation. Adding support for checking that unwrapped data is valid.auto_magic
Diffstat (limited to 'src/rtl/keywrap_core.v')
-rw-r--r--src/rtl/keywrap_core.v42
1 files changed, 35 insertions, 7 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index d1e63b0..469a238 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -52,7 +52,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
output wire ready,
output wire valid,
- input wire [(MEM_BITS - 2) : 0] rlen,
+ input wire [(LEN_BITS - 1) : 0] length,
input wire [255 : 0] key,
input wire keylen,
@@ -84,6 +84,10 @@ module keywrap_core #(parameter MEM_BITS = 11)
localparam CTRL_NEXT_UCHECK = 4'h9;
localparam CTRL_NEXT_FINALIZE = 4'ha;
+ localparam LEN_BITS = MEM_BITS + 2;
+
+ localparam AIV = 32'ha65959a6;
+
//----------------------------------------------------------------
// Registers and memories including control signals.
@@ -134,6 +138,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
reg update_state;
+ reg [(MEM_BITS - 1) : 0] rlen;
+
reg core_we;
reg [(MEM_BITS - 2) : 0] core_addr;
reg [63 : 0] core_wr_data;
@@ -238,7 +244,13 @@ module keywrap_core #(parameter MEM_BITS = 11)
core_addr = block_ctr_reg;
core_we = 1'h0;
- xor_val = (rlen * iteration_ctr_reg) + {51'h0, (block_ctr_reg + 1'h1)};
+ // Calculate the correct number of blocks including padding.
+ if (length[1 : 0] === 2'h0)
+ rlen = length[(LEN_BITS - 1) : 3];
+ else
+ rlen = length[(LEN_BITS - 2) : 3] + 1'b1;
+
+ xor_val = (rlen * iteration_ctr_reg) + {52'h0, (block_ctr_reg + 1'h1)};
if (encdec)
aes_block = {a_reg, core_rd_data};
@@ -249,8 +261,11 @@ module keywrap_core #(parameter MEM_BITS = 11)
if (init_a)
begin
- a_new = a_init;
a_we = 1'h1;
+ if (encdec)
+ a_new = {AIV, {{(32 - (MEM_BITS + 2)){1'b0}}, length}};
+ else
+ a_new = a_init;
end
if (update_state)
@@ -510,10 +525,23 @@ module keywrap_core #(parameter MEM_BITS = 11)
CTRL_NEXT_FINALIZE:
begin
- ready_new = 1'h1;
- ready_we = 1'h1;
- valid_new = 1'h1;
- valid_we = 1'h1;
+ ready_new = 1'h1;
+ ready_we = 1'h1;
+
+ if (encdec)
+ begin
+ valid_new = 1'h1;
+ valid_we = 1'h1;
+ end
+ else
+ begin
+ if (a_reg[63 : 32] == AIV)
+ begin
+ valid_new = 1'h1;
+ valid_we = 1'h1;
+ end
+ end
+
keywrap_core_ctrl_new = CTRL_IDLE;
keywrap_core_ctrl_we = 1'h1;
end