Performed Verilog parameter magic to make the design scaleable in terms of capacity. Does not yet work, but at least the linter is fairly happy.

1 files changed, 46 insertions, 48 deletions

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 6a28133..f55545f 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -4,6 +4,17 @@
 // --------
 // Top level wrapper for the KEY WRAP core.
 //
+// Since $clog2() is not supported by all tools, and constant
+// functions are not supported by some other tools we need to
+// do the size to number of bits calculation by hand.
+// 8192 bytes = 2048 32 bit words. This requires 11 bits.
+// We need additional space for control and status words. But
+// since we have filled the address space, we need another MSB
+// in the address. Thus ADDR_BITS = 12 bits.
+//
+// 0x000 - 0x7ff are for control and status.
+// 0x800 - 0xfff are for data storage
+//
 //
 // Author: Joachim Strombergson
 // Copyright (c) 2018, NORDUnet A/S
@@ -37,38 +48,19 @@
 //
 //======================================================================
 
-module keywrap(
-               // Clock and reset.
-               input wire           clk,
-               input wire           reset_n,
+module keywrap #(parameter ADDR_BITS = 15)
+               (
+                input wire                        clk,
+                input wire                        reset_n,
 
-               // Control.
-               input wire           cs,
-               input wire           we,
-
-               // Data ports.
-               input wire  [(ASPACE - 1) : 0] address,
-               input wire  [31 : 0] write_data,
-               output wire [31 : 0] read_data,
-               output wire          error
-              );
-
-  //----------------------------------------------------------------
-  // External parameters
-  //----------------------------------------------------------------
-  // Since $clog2() is not supported by all tools, and constant
-  // functions are not supported by some other tools we need to
-  // do the size to number of bits calculation by hand.
-  // 8192 bytes = 2048 32 bit words. This requires 11 bits.
-  // We need additional space for control and status words. But
-  // since we have filled the address space, we need another MSB
-  // in the address - 12 bits.
-  //
-  // 0x000 - 0x7ff are for control and status.
-  // 0x800 - 0xfff are for data storage
-  parameter ASPACE = 12;
-  localparam MEM_SPACE = (ASPACE / 2);
+                input wire                        cs,
+                input wire                        we,
 
+                input wire  [(ADDR_BITS - 1) : 0] address,
+                input wire  [31 : 0]              write_data,
+                output wire [31 : 0]              read_data,
+                output wire                       error
+               );
 
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
@@ -108,7 +100,11 @@ module keywrap(
 
   localparam CORE_NAME0       = 32'h6b657920; // "key "
   localparam CORE_NAME1       = 32'h77726170; // "wrap"
-  localparam CORE_VERSION     = 32'h302e3731; // "0.71"
+  localparam CORE_VERSION     = 32'h302e3830; // "0.80"
+
+
+  localparam MEM_BITS         = ADDR_BITS - 1;
+  localparam PAD              = ADDR_BITS - 8;
 
 
   //----------------------------------------------------------------
@@ -179,7 +175,8 @@ module keywrap(
   //----------------------------------------------------------------
   // core instantiation.
   //----------------------------------------------------------------
-  keywrap_core core(
+  keywrap_core #(.MEM_BITS(MEM_BITS))
+               core(
                     .clk(clk),
                     .reset_n(reset_n),
 
@@ -291,28 +288,29 @@ module keywrap(
         begin
           if (we)
             begin
-              if (address == ADDR_CTRL)
+              if (address == {{PAD{1'h0}}, ADDR_CTRL})
                 begin
                   init_new = write_data[CTRL_INIT_BIT];
                   next_new = write_data[CTRL_NEXT_BIT];
                 end
 
-              if (address == ADDR_CONFIG)
+              if (address == {{PAD{1'h0}}, ADDR_CONFIG})
                 config_we = 1'h1;
 
-              if (address == ADDR_RLEN)
+              if (address == {{PAD{1'h0}}, ADDR_RLEN})
                 rlen_we = 1'h1;
 
-              if (address == ADDR_R_BANK)
+              if (address == {{PAD{1'h0}}, ADDR_R_BANK})
                 r_bank_we = 1'h1;
 
-              if (address == ADDR_A0)
+              if (address == {{PAD{1'h0}}, ADDR_A0})
                 a0_we = 1'h1;
 
-              if (address == ADDR_A1)
+              if (address == {{PAD{1'h0}}, ADDR_A1})
                 a1_we = 1'h1;
 
-              if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
+              if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) &&
+                   (address <= {{PAD{1'h0}}, ADDR_KEY7}))
                 key_we = 1'h1;
 
               if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
@@ -321,31 +319,31 @@ module keywrap(
           else
             begin
               // Read access
-              if (address == ADDR_NAME0)
+              if (address == {{PAD{1'h0}}, ADDR_NAME0})
                 api_rd_delay_new = CORE_NAME0;
 
-              if (address == ADDR_NAME1)
+              if (address == {{PAD{1'h0}}, ADDR_NAME1})
                 api_rd_delay_new = CORE_NAME1;
 
-              if (address == ADDR_VERSION)
+              if (address == {{PAD{1'h0}}, ADDR_VERSION})
                 api_rd_delay_new = CORE_VERSION;
 
-              if (address == ADDR_CTRL)
+              if (address == {{PAD{1'h0}}, ADDR_CTRL})
                 api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
 
-              if (address == ADDR_STATUS)
+              if (address == {{PAD{1'h0}}, ADDR_STATUS})
                 api_rd_delay_new = {30'h0, valid_reg, ready_reg};
 
-              if (address == ADDR_RLEN)
+              if (address == {{PAD{1'h0}}, ADDR_RLEN})
                 api_rd_delay_new = {19'h0, rlen_reg};
 
-              if (address == ADDR_R_BANK)
+              if (address == {{PAD{1'h0}}, ADDR_R_BANK})
                 api_rd_delay_new = {25'h0, r_bank_reg};
 
-              if (address == ADDR_A0)
+              if (address == {{PAD{1'h0}}, ADDR_A0})
                 api_rd_delay_new = core_a_result[63 : 32];
 
-              if (address == ADDR_A1)
+              if (address == {{PAD{1'h0}}, ADDR_A1})
                 api_rd_delay_new = core_a_result[31 : 0];
             end // else: !if(we)
         end // if (cs)