//======================================================================
//
// fpga_mkm_spi_slave.v
// --------------------
// SPI Slave for the FPGA based Master Key Memory (MKM).
//
// The interface captures serial data from the master and provides
// it as bytes to the interface host. Any response from the host
// to be transmitted to the master should be given as bytes.
//
// It is the responsibility of the host to send as much response as
// the master expects.
//
// The clk driving the interface must be >> sclk to allow for
// the cycles needed to perform state handling, parsing etc.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2019, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module fpga_mkm_spi_slave(
                          input wire          clk,

                          input wire          ss,
                          input wire          sclk,
                          input wire          mosi,
                          output wire         miso,

                          output wire         spi_active,
                          output wire         rx_byte_available,
                          output wire [7 : 0] rx_byte,

                          input wire          tx_byte_load,
                          input wire [7 : 0]  tx_byte
                         );


  //----------------------------------------------------------------
  // Internal constant and parameter definitions.
  //----------------------------------------------------------------
  localparam CTRL_IDLE     = 3'h0;
  localparam CTRL_SELECTED = 3'h1;
  localparam CTRL_POS_EDGE = 3'h2;
  localparam CTRL_NEG_EDGE = 3'h3;


  //----------------------------------------------------------------
  // Registers including update variables and write enable.
  //----------------------------------------------------------------
  reg         ss_sample0_reg;
  reg         ss_sample1_reg;
  reg         ss_reg;

  reg         sclk_sample0_reg;
  reg         sclk_sample1_reg;
  reg         sclk_reg;

  reg         mosi_sample0_reg;
  reg         mosi_sample1_reg;
  reg         mosi_reg;

  reg [7 : 0] rx_byte_reg = 8'h0;
  reg [7 : 0] rx_byte_new;
  reg         rx_byte_next;

  reg [7 : 0] tx_byte_reg = 8'h0;
  reg [7 : 0] tx_byte_new;
  reg         tx_byte_we;
  reg         tx_byte_next;
  reg         tx_byte_loadz;

  reg [2 : 0] bit_ctr_reg = 3'h0;
  reg [2 : 0] bit_ctr_new;
  reg         bit_ctr_we;
  reg         bit_ctr_rst;
  reg         bit_ctr_inc;

  reg         spi_active_reg = 1'h0;
  reg         spi_active_new;
  reg         spi_active_we;

  reg [2 : 0] spi_slave_ctrl_reg = CTRL_IDLE;
  reg [2 : 0] spi_slave_ctrl_new;
  reg         spi_slave_ctrl_we;


  //----------------------------------------------------------------
  // Concurrent connectivity for ports etc.
  //----------------------------------------------------------------
  assign miso              = tx_byte_reg[7];
  assign rx_byte_available = (bit_ctr_reg == 3'h7);
  assign rx_byte           = rx_byte_reg;
  assign spi_active        = spi_active_reg;


  //----------------------------------------------------------------
  // reg_update
  //----------------------------------------------------------------
  always @ (posedge clk)
    begin : reg_update
      ss_sample0_reg <= ss;
      ss_sample1_reg <= ss_sample0_reg;
      ss_reg         <= ss_sample1_reg;

      sclk_sample0_reg <= sclk;
      sclk_sample1_reg <= sclk_sample0_reg;
      sclk_reg         <= sclk_sample1_reg;

      mosi_sample0_reg <= mosi;
      mosi_sample1_reg <= mosi_sample0_reg;
      mosi_reg         <= mosi_sample1_reg;

      if (rx_byte_next)
        rx_byte_reg <= {rx_byte_reg[6 : 0], mosi_reg};

      if (bit_ctr_we)
        bit_ctr_reg <= bit_ctr_new;

      if (tx_byte_we)
        tx_byte_reg <= tx_byte_new;

      if (spi_active_we)
        spi_active_reg <= spi_active_new;

      if (spi_slave_ctrl_we)
        spi_slave_ctrl_reg <= spi_slave_ctrl_new;
    end


  //----------------------------------------------------------------
  // tx_byte_logic
  // Update the tx_byte register. Either loading or shifting to
  // set the next bit to transmit.
  //----------------------------------------------------------------
  always @*
    begin : tx_byte_logic
      tx_byte_new = 8'h0;
      tx_byte_we  = 1'h0;

      if (tx_byte_load)
        begin
          tx_byte_new = tx_byte;
          tx_byte_we  = 1'h1;
        end

      if (tx_byte_loadz)
        begin
          tx_byte_new = 8'h0;
          tx_byte_we  = 1'h1;
        end

      if (tx_byte_next)
        begin
          tx_byte_new = {tx_byte_reg[6 : 0], 1'h0};
          tx_byte_we  = 1'h1;
        end
    end


  //----------------------------------------------------------------
  // bit_ctr
  //----------------------------------------------------------------
  always @*
    begin : bit_ctr
      bit_ctr_new = 3'h0;
      bit_ctr_we  = 1'h0;

      if (bit_ctr_rst)
        begin
          bit_ctr_new = 3'h0;
          bit_ctr_we  = 1'h1;
        end

      if (bit_ctr_inc)
        begin
          bit_ctr_new = bit_ctr_reg + 1'h1;
          bit_ctr_we  = 1'h1;
        end
    end


  //----------------------------------------------------------------
  // spi_slave_ctrl_fsm
  //----------------------------------------------------------------
  always @*
    begin : spi_slave_ctrl_fsm
      bit_ctr_rst        = 1'h0;
      bit_ctr_inc        = 1'h0;
      rx_byte_next       = 1'h0;
      tx_byte_loadz      = 1'h0;
      tx_byte_next       = 1'h0;
      spi_active_new     = 1'h0;
      spi_active_we      = 1'h0;
      spi_slave_ctrl_new = CTRL_IDLE;
      spi_slave_ctrl_we  = 1'h0;

      case (spi_slave_ctrl_reg)
        CTRL_IDLE:
          begin
            if (ss_reg == 0)
              begin
                spi_slave_ctrl_new = CTRL_SELECTED;
                spi_slave_ctrl_we  = 1'h1;
              end
          end


        CTRL_SELECTED:
          begin
            bit_ctr_rst    = 1'h1;
            tx_byte_loadz  = 1'h1;
            spi_active_new = 1'h1;
            spi_active_we  = 1'h1;
            spi_slave_ctrl_new = CTRL_POS_EDGE;
            spi_slave_ctrl_we  = 1'h1;
          end


        CTRL_POS_EDGE:
          begin
            if (ss_reg == 0)
              begin
                if ((sclk_sample1_reg == 1'h1) && (sclk_reg == 1'h0))
                  begin
                    rx_byte_next       = 1'h1;
                    tx_byte_next       = 1'h1;
                    bit_ctr_inc        = 1'h1;
                    spi_slave_ctrl_new = CTRL_NEG_EDGE;
                    spi_slave_ctrl_we  = 1'h1;
                  end
              end
            else
              begin
                spi_active_new     = 1'h0;
                spi_active_we      = 1'h1;
                spi_slave_ctrl_new = CTRL_IDLE;
                spi_slave_ctrl_we  = 1'h1;
              end
          end


        CTRL_NEG_EDGE:
          begin
            if (ss_reg == 0)
              begin
                if ((sclk_sample1_reg == 1'h0) && (sclk_reg == 1'h1))
                  begin
                    spi_slave_ctrl_new = CTRL_POS_EDGE;
                    spi_slave_ctrl_we  = 1'h1;
                  end
              end
            else
              begin
                spi_active_new     = 1'h0;
                spi_active_we      = 1'h1;
                spi_slave_ctrl_new = CTRL_IDLE;
                spi_slave_ctrl_we  = 1'h1;
              end
          end
      endcase // case (spi_slave_ctrl_reg)
    end // block: spi_slave_ctrl_fsm

endmodule // fpga_mkm_spi_slave

//======================================================================
// EOF fpga_mkm_spi_slave.v
//======================================================================