From 6f167e358cd681722eea2b482e2e8d429ea673ad Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@assured.se>
Date: Tue, 26 Mar 2019 14:49:45 +0100
Subject: Completed first RTL for the SPI slave. Simplified the design to
 simply be two shift registers and a somple FSM that detects clock flanks and
 SS.

---
 toolruns/Makefile | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

(limited to 'toolruns')

diff --git a/toolruns/Makefile b/toolruns/Makefile
index bb1f4bf..82f2de3 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -55,6 +55,9 @@ FOOTPRINT = tq144
 TOP_NAME = fpga_mkm
 TOP_SRC = ../src/rtl/fpga_mkm.v
 TB_TOP_SRC = ../src/tb/tb_fpga_mkm.v
+SPI_SRC = ../src/rtl/fpga_mkm_spi_slave.v
+TB_SPI_SRC = ../src/tb/tb_fpga_mkm_spi_slave.v
+
 CONFIG_SRC = ../src/config/pinmap_icestick.pcf
 
 CC = iverilog
@@ -70,19 +73,19 @@ LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 all: top.sim
 
 
-top.sim: $(TB_TOP_SRC) $(TOP_SRC)
-	$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC)
+top.sim: $(TB_TOP_SRC) $(TOP_SRC) $(SPI_SRC)
+	$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) $(SPI_SRC)
 
 
 sim-top: top.sim
 	./top.sim
 
 
-lint:  $(TOP_SRC)
-	$(LINT) $(LINT_FLAGS) $(TOP_SRC)
+lint:  $(TOP_SRC) $(SPI_SRC)
+	$(LINT) $(LINT_FLAGS) $(TOP_SRC) $(SPI_SRC)
 
 
-bitstream: $(TOP_SRC)
+bitstream: $(TOP_SRC) $(SPI_SRC)
 	mkdir -p $(BUILD)
 	yosys -p "synth_ice40 -top $(TOP_NAME) -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC)
 	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p $(CONFIG_SRC) $(BUILD)/$(PROJ).blif
-- 
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