From ea442d768cba08d3728ea2e7e62f1d90e0e781fd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@assured.se>
Date: Tue, 12 Feb 2019 10:41:53 +0100
Subject: (1) Fixed Makefile. Now we can build sim target, generate bitstream
 and also burn it to the FPGA dev board. (2) Started structuring the RTL
 source file.

---
 src/rtl/fpga_mkm.v | 30 +++++++++++++++++++++---------
 toolruns/Makefile  | 46 +++++++++++++++++++++++-----------------------
 2 files changed, 44 insertions(+), 32 deletions(-)

diff --git a/src/rtl/fpga_mkm.v b/src/rtl/fpga_mkm.v
index 133a3f8..de96ffa 100644
--- a/src/rtl/fpga_mkm.v
+++ b/src/rtl/fpga_mkm.v
@@ -37,25 +37,37 @@
 //
 //======================================================================
 
-module fpga_mkm (
-                 input wire clk_in,
-                 output wire rled1,
-                 output wire rled2,
-                 output wire rled3,
-                 output wire rled4,
-                 output wire gled5
-                );
+module fpga_mkm(
+                input wire clk_in,
 
+                output wire rled1,
+                output wire rled2,
+                output wire rled3,
+                output wire rled4,
+                output wire gled5
+               );
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
   reg [31 : 0] counter_reg = 32'b0;
 
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
   assign rled1 = counter_reg[21];
   assign rled2 = counter_reg[22];
   assign rled3 = counter_reg[23];
   assign rled4 = counter_reg[24];
   assign gled5 = counter_reg[25];
 
+
+  //----------------------------------------------------------------
+  // reg_update
+  //----------------------------------------------------------------
   always @ (posedge clk_in)
-    begin
+    begin : reg_update
       counter_reg <= counter_reg + 1;
     end
 
diff --git a/toolruns/Makefile b/toolruns/Makefile
index b95b3cc..e056830 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -45,9 +45,10 @@ BUILD     = ./build
 DEVICE    = 1k
 FOOTPRINT = tq144
 
-TOP_SRC= ../src/rtl/fpga_mkm.v
+TOP_NAME = fpga_mkm
+TOP_SRC = ../src/rtl/fpga_mkm.v
 TB_TOP_SRC = ../src/tb/tb_fpga_mkm.v
-CONFIG_SRC= ../src/config/pinmap.pcf
+CONFIG_SRC = ../src/config/pinmap_icestick.pcf
 
 CC = iverilog
 CC_FLAGS = -Wall
@@ -55,10 +56,13 @@ CC_FLAGS = -Wall
 LINT = verilator
 LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
 
-.PHONY: all implement burn
+
+.PHONY: all bitstream burn
+
 
 all: top.sim
 
+
 top.sim: $(TB_TOP_SRC) $(TOP_SRC)
 	$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC)
 
@@ -71,38 +75,34 @@ lint:  $(TOP_SRC)
 	$(LINT) $(LINT_FLAGS) $(TOP_SRC)
 
 
-clean:
-	rm -f *.sim
-	rm build/*
-
-
-implement: $(TOP_SRC)
-	# if build folder doesn't exist, create it
+bitstream: $(TOP_SRC)
 	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
+	yosys -p "synth_ice40 -top $(TOP_NAME) -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC)
+	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p $(CONFIG_SRC) $(BUILD)/$(PROJ).blif
 	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
 
 
-burn:	$(PROJ).bin
+burn:
 	iceprog $(BUILD)/$(PROJ).bin
 
 
+clean:
+	rm -f *.sim
+	rm -rf build
+
+
 help:
 	@echo "Build system for simulation of AES Verilog core"
 	@echo ""
 	@echo "Supported targets:"
 	@echo "------------------"
-	@echo "all:          Build all simulation targets."
-	@echo "lint:         Lint all rtl source files."
-	@echo "top.sim:      Build top level simulation target."
-	@echo "sim-top:      Run top level simulation."
-	@echo "implement:    Implement design for the FPGA."
-	@echo "burn:         Write bitstream to FPGA config mem.."
-	@echo "clean:        Delete all built files."
+	@echo "all:       Build all simulation targets."
+	@echo "lint:      Lint all rtl source files."
+	@echo "top.sim:   Build top level simulation target."
+	@echo "sim-top:   Run top level simulation."
+	@echo "bitstream: Generate FPGA bitstream."
+	@echo "burn:      Write bitstream to FPGA config mem.."
+	@echo "clean:     Delete all built files and directories."
 
 #===================================================================
 # EOF Makefile
-- 
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