From 87bd28c78677f1b61f9a10ddd8db2f3cc7bf7fae Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@assured.se>
Date: Tue, 5 Feb 2019 11:08:38 +0100
Subject: Adding LICENSE and initial version of README.txt with a short
 description of what the core will be.

---
 LICENSE   | 29 +++++++++++++++++++++++++++++
 README.md | 30 ++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 LICENSE
 create mode 100644 README.md

diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..65e4e7e
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,29 @@
+Author: Joachim Strömbergson
+Copyright (c) 2019, NORDUnet A/S
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+- Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+- Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+- Neither the name of the NORDUnet nor the names of its contributors may
+  be used to endorse or promote products derived from this software
+  without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..c0cdfce
--- /dev/null
+++ b/README.md
@@ -0,0 +1,30 @@
+fpga-mkm
+=========
+## Introduction ##
+This core implements a FPGA based, active Master Key Memory (MKM).
+
+The memory provides access control, anti-remanence functionality and
+tamper detection protection with ns zeriosation latency.
+
+The target FPGA family is the Lattice iCE40 that can be kept in stand-by
+with a small battery. The target design flow is the
+[http://www.clifford.at/icestorm/ "Project IceStorm"] fully open source
+Verilog-to-Bitstream flow for iCE40 FPGAs.
+
+The core provides a SPI slave interface for connectivity and one or more
+tamper event inputs. Finally there might be a LED that provides
+status. At least during debugging.
+
+
+
+## Status ##
+Spec is being developed. Core not implemented. Does NOT work.
+
+
+
+## Implementation details
+
+
+
+## Implementation results
+TBW.
-- 
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