From 681c311e98b704b383bdca67f569a206fad551a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 11 Feb 2019 20:27:09 +0100 Subject: Fixed Makefile to allow building of simulation executable, linting and FPGA bitstream. Updated code to work. --- src/rtl/fpga_mkm.v | 66 +++++++++++++++++++++++++++++++ src/rtl/top.v | 23 ----------- src/tb/tb_fpga_mkm.v | 0 toolruns/Makefile | 109 +++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+), 23 deletions(-) create mode 100644 src/rtl/fpga_mkm.v delete mode 100644 src/rtl/top.v create mode 100644 src/tb/tb_fpga_mkm.v create mode 100755 toolruns/Makefile diff --git a/src/rtl/fpga_mkm.v b/src/rtl/fpga_mkm.v new file mode 100644 index 0000000..133a3f8 --- /dev/null +++ b/src/rtl/fpga_mkm.v @@ -0,0 +1,66 @@ +//====================================================================== +// +// fpga_mkm.v +// ---------- +// Top level module for the FPGA based Master Key Memory (MKM). +// +// +// Author: Joachim Strombergson +// Copyright (c) 2019, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module fpga_mkm ( + input wire clk_in, + output wire rled1, + output wire rled2, + output wire rled3, + output wire rled4, + output wire gled5 + ); + + reg [31 : 0] counter_reg = 32'b0; + + assign rled1 = counter_reg[21]; + assign rled2 = counter_reg[22]; + assign rled3 = counter_reg[23]; + assign rled4 = counter_reg[24]; + assign gled5 = counter_reg[25]; + + always @ (posedge clk_in) + begin + counter_reg <= counter_reg + 1; + end + +endmodule // fpga_mkm + +//====================================================================== +// EOF fpga_mkm.v +//====================================================================== diff --git a/src/rtl/top.v b/src/rtl/top.v deleted file mode 100644 index 58daeb2..0000000 --- a/src/rtl/top.v +++ /dev/null @@ -1,23 +0,0 @@ -module top ( - input wire clk_in, - output wire rled1, - output wire rled2, - output wire rled3, - output wire rled4, - output wire gled5 - ); - - reg [31 : 0] counter_reg = 32'b0; - - assign rled1 = counter[21]; - assign rled2 = counter[22]; - assign rled3 = counter[23]; - assign rled4 = counter[24]; - assign gled5 = counter[25]; - - always @ (posedge hwclk) - begin - counter_reg <= counter_reg + 1; - end - -endmodule // top diff --git a/src/tb/tb_fpga_mkm.v b/src/tb/tb_fpga_mkm.v new file mode 100644 index 0000000..e69de29 diff --git a/toolruns/Makefile b/toolruns/Makefile new file mode 100755 index 0000000..b95b3cc --- /dev/null +++ b/toolruns/Makefile @@ -0,0 +1,109 @@ +#=================================================================== +# +# Makefile +# -------- +# Makefile for building, simlating and programming the the fpga_mkm +# core. Note that the target device is a Lattice iCEstick +# Evaluation Kit. +# +# +# Author: Joachim Strombergson +# Copyright (c) 2019, NORDUnet A/S +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of the NORDUnet nor the names of its contributors may +# be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#=================================================================== + +# Project defines +PROJ = fpga_mkm +BUILD = ./build +DEVICE = 1k +FOOTPRINT = tq144 + +TOP_SRC= ../src/rtl/fpga_mkm.v +TB_TOP_SRC = ../src/tb/tb_fpga_mkm.v +CONFIG_SRC= ../src/config/pinmap.pcf + +CC = iverilog +CC_FLAGS = -Wall + +LINT = verilator +LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME + +.PHONY: all implement burn + +all: top.sim + +top.sim: $(TB_TOP_SRC) $(TOP_SRC) + $(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) + + +sim-top: top.sim + ./top.sim + + +lint: $(TOP_SRC) + $(LINT) $(LINT_FLAGS) $(TOP_SRC) + + +clean: + rm -f *.sim + rm build/* + + +implement: $(TOP_SRC) + # if build folder doesn't exist, create it + mkdir -p $(BUILD) + # synthesize using Yosys + yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC) + # Place and route using arachne + arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif + # Convert to bitstream using IcePack + icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin + + +burn: $(PROJ).bin + iceprog $(BUILD)/$(PROJ).bin + + +help: + @echo "Build system for simulation of AES Verilog core" + @echo "" + @echo "Supported targets:" + @echo "------------------" + @echo "all: Build all simulation targets." + @echo "lint: Lint all rtl source files." + @echo "top.sim: Build top level simulation target." + @echo "sim-top: Run top level simulation." + @echo "implement: Implement design for the FPGA." + @echo "burn: Write bitstream to FPGA config mem.." + @echo "clean: Delete all built files." + +#=================================================================== +# EOF Makefile +#=================================================================== -- cgit v1.2.3