From 3ad18f9945aa0f6a617fcd399a0a402db9a28027 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 9 Apr 2019 16:10:55 +0200 Subject: Adding inital tb for the SPI slave. Debugging the SPI slave and the FPGA_MKM. --- src/rtl/fpga_mkm.v | 46 ++++++---- src/rtl/fpga_mkm_spi_slave.v | 5 +- src/tb/tb_fpga_mkm.v | 6 +- src/tb/tb_fpga_mkm_spi_slave.v | 192 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 227 insertions(+), 22 deletions(-) create mode 100644 src/tb/tb_fpga_mkm_spi_slave.v diff --git a/src/rtl/fpga_mkm.v b/src/rtl/fpga_mkm.v index 89825ed..38517e6 100644 --- a/src/rtl/fpga_mkm.v +++ b/src/rtl/fpga_mkm.v @@ -86,9 +86,9 @@ module fpga_mkm( reg [21 : 0] alarm_counter_reg = 22'h0; - reg alarm_reg = 1'h0; - reg alarm_new; - reg alarm_we; + reg tamper_reg = 1'h0; + reg tamper_new; + reg tamper_we; reg key_loaded_reg = 1'h0; reg key_loaded_new; @@ -100,6 +100,14 @@ module fpga_mkm( reg [1 : 0] fpga_mkm_ctrl_new; reg fpga_mkm_ctrl_we; + wire spi_active; + wire rx_byte_available; + wire [7 : 0] rx_byte; + reg tx_byte_load; + reg [7 : 0] tx_byte_reg; + reg [7 : 0] tx_byte_new; + reg tx_byte_we; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -111,7 +119,6 @@ module fpga_mkm( assign gled5 = key_loaded_reg; - //---------------------------------------------------------------- // Module instantiations. //---------------------------------------------------------------- @@ -121,11 +128,11 @@ module fpga_mkm( .sclk(sclk), .mosi(mosi), .miso(miso), - .spi_active(), - .rx_byte_available(), - .rx_byte(), - .tx_byte_load(), - .tx_byte() + .spi_active(spi_active), + .rx_byte_available(rx_byte_available), + .rx_byte(rx_byte), + .tx_byte_load(tx_byte), + .tx_byte(tx_byte_reg) ); @@ -138,15 +145,18 @@ module fpga_mkm( if (!tamper) begin - for (i = 0 ; i < MEM_WORDS ; i = i + 1) - key_mem[i] <= 32'h0; + for (i = 0 ; i < MEM_BYTES ; i = i + 1) + key_mem[i] <= 8'h0; + + key_loaded_reg <= 1'h0; + tamper_reg <= 1'h1; end else begin alarm_counter_reg <= alarm_counter_reg + 1; - if (alarm_we) - alarm_reg <= alarm_new; + if (tamper_we) + tamper_reg <= tamper_new; if (key_loaded_we) key_loaded_reg <= key_loaded_new; @@ -162,8 +172,8 @@ module fpga_mkm( //---------------------------------------------------------------- always @* begin : fpga_mkm_ctrl_fsm - alarm_new = 1'h0; - alarm_we = 1'h0; + tamper_new = 1'h0; + tamper_we = 1'h0; key_loaded_new = 1'h0; key_loaded_we = 1'h0; fpga_mkm_ctrl_new = CTRL_IDLE; @@ -173,14 +183,16 @@ module fpga_mkm( CTRL_IDLE: begin - if (tamper) + if (spi_active) begin - fpga_mkm_ctrl_new = CTRL_ALARM; + fpga_mkm_ctrl_new = CTRL_CMD; fpga_mkm_ctrl_we = 1'h1; end end + + CTRL_ALARM: begin diff --git a/src/rtl/fpga_mkm_spi_slave.v b/src/rtl/fpga_mkm_spi_slave.v index 1449af2..9a59f9e 100644 --- a/src/rtl/fpga_mkm_spi_slave.v +++ b/src/rtl/fpga_mkm_spi_slave.v @@ -59,8 +59,9 @@ module fpga_mkm_spi_slave( output wire rx_byte_available, output wire [7 : 0] rx_byte, - input wire tx_byte_load, - input wire [7 : 0] tx_byte + input wire tx_byte_available, + input wire [7 : 0] tx_byte, + output wire tx_byte_ack ); diff --git a/src/tb/tb_fpga_mkm.v b/src/tb/tb_fpga_mkm.v index 682a99d..226380c 100644 --- a/src/tb/tb_fpga_mkm.v +++ b/src/tb/tb_fpga_mkm.v @@ -37,7 +37,7 @@ // //====================================================================== -module tb_fpga_mklm(); +module tb_fpga_mkm(); //---------------------------------------------------------------- // Parameters. @@ -96,7 +96,7 @@ module tb_fpga_mklm(); //---------------------------------------------------------------- always begin : clk_gen - #CLK_HALF_PERIOD; + #(CLK_HALF_PERIOD); tb_clk = !tb_clk; end // clk_gen @@ -185,7 +185,7 @@ module tb_fpga_mklm(); $finish; end -endmodule // tb_keywrap_core +endmodule // tb_fpga_mkm //====================================================================== // EOF tb_fpga_mkm.v diff --git a/src/tb/tb_fpga_mkm_spi_slave.v b/src/tb/tb_fpga_mkm_spi_slave.v new file mode 100644 index 0000000..d29aa40 --- /dev/null +++ b/src/tb/tb_fpga_mkm_spi_slave.v @@ -0,0 +1,192 @@ +//====================================================================== +// +// tb_fpga_mkm_spi_slave.v +// ----------------------- +// Testbench for the SPI slave interface for the FPGA based +// Master Key Memory (MKM). +// +// +// Author: Joachim Strombergson +// Copyright (c) 2019, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module tb_fpga_mkm_spi_slave(); + + //---------------------------------------------------------------- + // Parameters. + //---------------------------------------------------------------- + parameter DEBUG = 1; + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + + //---------------------------------------------------------------- + // Variables, regs and wires. + //---------------------------------------------------------------- + integer cycle_ctr; + integer error_ctr; + integer tc_ctr; + + reg tb_clk; + reg tb_ss; + reg tb_sclk; + reg tb_mosi; + wire tb_miso; + wire tb_spi_active; + wire tb_rx_byte_available; + wire [7 : 0] tb_rx_byte; + reg tb_tx_byte_available; + reg [7 : 0] tb_tx_byte; + wire tb_tx_byte_ack; + + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + fpga_mkm_spi_slave dut( + .clk(tb_clk), + .ss(tb_ss), + .sclk(tb_sclk), + .mosi(tb_mosi), + .miso(tb_miso), + + .spi_active(tb_spi_active), + .rx_byte_available(tb_rx_byte_available), + .rx_byte(tb_rx_byte), + + .tx_byte_available(tb_tx_byte_available), + .tx_byte(tb_tx_byte), + .tx_byte_ack(tb_tx_byte_ack) + ); + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #(CLK_HALF_PERIOD); + tb_clk = !tb_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + cycle_ctr = cycle_ctr + 1; + #(CLK_PERIOD); + end + + + //---------------------------------------------------------------- + // display_test_results() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_results; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully", tc_ctr); + end + else + begin + $display("*** %02d tests completed - %02d test cases did not complete successfully.", + tc_ctr, error_ctr); + end + end + endtask // display_test_results + + + //---------------------------------------------------------------- + // init_sim + // + // Initialize DUT inputs, test case counters, clock etc. + //---------------------------------------------------------------- + task init_sim; + begin : init_sim + cycle_ctr = 0; + error_ctr = 0; + tc_ctr = 0; + + tb_clk = 1'h0; + tb_ss = 1'h1; + tb_sclk = 1'h0; + tb_mosi = 1'h0; + end + endtask // init_sim + + + //---------------------------------------------------------------- + // wait_cycles + //---------------------------------------------------------------- + task wait_cycles (input integer cycles); + begin : wait_cycles + #(cycles); + end + endtask // wait_cycles + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + initial + begin + $display(" -= Testbench for fpga_mkm_spi_slave started =-"); + $display(" ============================================="); + $display(""); + + init_sim(); + wait_cycles(100); + display_test_results(); + + $display(""); + $display(" -= Testbench for fpga_mkm_spi_slave completed =-"); + $display(" ==============================================="); + $finish; + end + +endmodule // tb_fpga_mkm_spi_slave + +//====================================================================== +// EOF tb_fpga_mkm_spi_slave.v +//====================================================================== -- cgit v1.2.3