| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-02-12 | (1) Fixed Makefile. Now we can build sim target, generate bitstream and also ↵ | Joachim Strömbergson | |
| burn it to the FPGA dev board. (2) Started structuring the RTL source file. | |||
| 2019-02-11 | Fixed Makefile to allow building of simulation executable, linting and FPGA ↵ | Joachim Strömbergson | |
| bitstream. Updated code to work. | |||
| 2019-02-11 | Adding initial version of top. | Joachim Strömbergson | |
| 2019-02-11 | Adding pinmap for the iCEstick. | Joachim Strömbergson | |
| 2019-02-05 | Adding LICENSE and initial version of README.txt with a short description of ↵ | Joachim Strömbergson | |
| what the core will be. | |||
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index : user/js/fpga_mkm | |
| FPGA-based active Master Key Memory (MKM) | git repositories |
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