diff options
| author | Joachim StroĢmbergson <joachim@assured.se> | 2019-03-26 14:49:45 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@assured.se> | 2019-03-26 14:49:45 +0100 |
| commit | 6f167e358cd681722eea2b482e2e8d429ea673ad (patch) | |
| tree | 252076418109ded708366d6155664c5c655b61d6 /toolruns | |
| parent | 47945186ff63e134ff393e4b433d4b7162a4bbda (diff) | |
Completed first RTL for the SPI slave. Simplified the design to simply be two shift registers and a somple FSM that detects clock flanks and SS.
Diffstat (limited to 'toolruns')
| -rwxr-xr-x | toolruns/Makefile | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile index bb1f4bf..82f2de3 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -55,6 +55,9 @@ FOOTPRINT = tq144 TOP_NAME = fpga_mkm TOP_SRC = ../src/rtl/fpga_mkm.v TB_TOP_SRC = ../src/tb/tb_fpga_mkm.v +SPI_SRC = ../src/rtl/fpga_mkm_spi_slave.v +TB_SPI_SRC = ../src/tb/tb_fpga_mkm_spi_slave.v + CONFIG_SRC = ../src/config/pinmap_icestick.pcf CC = iverilog @@ -70,19 +73,19 @@ LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME all: top.sim -top.sim: $(TB_TOP_SRC) $(TOP_SRC) - $(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) +top.sim: $(TB_TOP_SRC) $(TOP_SRC) $(SPI_SRC) + $(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC) $(SPI_SRC) sim-top: top.sim ./top.sim -lint: $(TOP_SRC) - $(LINT) $(LINT_FLAGS) $(TOP_SRC) +lint: $(TOP_SRC) $(SPI_SRC) + $(LINT) $(LINT_FLAGS) $(TOP_SRC) $(SPI_SRC) -bitstream: $(TOP_SRC) +bitstream: $(TOP_SRC) $(SPI_SRC) mkdir -p $(BUILD) yosys -p "synth_ice40 -top $(TOP_NAME) -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC) arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p $(CONFIG_SRC) $(BUILD)/$(PROJ).blif |