/* * core.c * ------ * This module contains code to probe the FPGA for its installed cores. * * Author: Paul Selkirk, Rob Austein * Copyright (c) 2015, NORDUnet A/S All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * - Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * - Neither the name of the NORDUnet nor the names of its contributors may * be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "hal.h" #include "hal_internal.h" /* * Each Cryptech core has a set of 4-byte registers, which are accessed * through a 16-bit address. The address space is divided as follows: * 3 bits segment selector | up to 8 segments * 5 bits core selector | up to 32 cores/segment (see note below) * 8 bits register selector | up to 256 registers/core (see modexp below) * * i.e, the address is structured as: * sss ccccc rrrrrrrr * * The I2C and UART communication channels use this 16-bit address format * directly in their read and write commands. * * The EIM communications channel translates this 16-bit address into a * 32-bit memory-mapped address in the range 0x08000000..807FFFF: * 00001000000000 sss 0 ccccc rrrrrrrr 00 * * EIM, as implemented on the Novena, uses a 19-bit address space: * Bits 18..16 are the semgent selector. * Bits 15..10 are the core selector. * Bits 9..2 are the register selector. * Bits 1..0 are zero, because reads and writes are always word aligned. * * Note that EIM can support 64 cores per segment, but we sacrifice one bit * in order to map it into a 16-bit address space. */ /* * Structure of our internal database is private, in case we want to * be change representation (array, tree, list of lists, whatever) at * some later date without having to change the public API. */ struct hal_core { hal_core_info_t info; struct hal_core *next; }; /* * Check whether a core's name matches a particular string. This is a * bit nasty due to non-null-terminated fixed-length names. */ static int name_matches(const hal_core_t *const core, const char * const name) { return (core != NULL && name != NULL && *name != '\0' && strncmp(name, core->info.name, strnlen(name, sizeof(core->info.name))) == 0); } /* * Probe the FPGA and build our internal database. * * At the moment this knows far more than it should about pecularities * of certain cores. In theory at least some of this will be fixed * soon on the Verilog side. Adding a core-length word to the core * header sure would make this simpler. */ #define CORE_MIN 0 #define CORE_MAX 0x10000 #define CORE_SIZE 0x100 /* Extra space to leave after particular cores. Yummy. */ static const struct { const char *name; hal_addr_t extra; } gaps[] = { { "csprng", 11 * CORE_SIZE }, /* empty slots after csprng */ { "modexps6", 3 * CORE_SIZE }, /* ModexpS6 uses four slots */ { "modexpa7", 3 * CORE_SIZE }, /* M
(module C_1210 (layer F.Cu) (tedit 4289BEAB)
  (attr smd)
  (fp_text reference C210 (at 0 0) (layer B.SilkS) hide
    (effects (font (size 1.524 1.524) (thickness 0.05)) (justify mirror))
  )
  (fp_text value "1210 CAPACITOR X5R 6.3V" (at 0 0) (layer Cmts.User)
    (effects (font (size 1.524 1.524) (thickness 0.05)))
  )
  (pad 1 smd rect (at 0 -1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask))
  (pad 2 smd rect (at 0 1.5 270) (size 1.6 2.6) (layers F.Cu F.Paste F.Mask))
  (model wrlshp/SW3dPS-CAPC3225.wrl
    (offset (xyz 1.249933981227875 0 1.250000021226883))
    (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158))
    (rotate (xyz 270 360 90))
  )
  (model wrlshp/F26EE9BE-B6B0.wrl
    (at (xyz 0 0 0))
    (scale (xyz 1 1 1))
    (rotate (xyz 0 0 180))
  )
)
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-17 21:40:45 +0000