From c97830fa39c95ee9edf2d8413d9e5f49b27bc7d7 Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Tue, 8 May 2018 16:11:45 +0200 Subject: commit all the label changes made by current fix-label.py --- rev03-KiCad/rev02_19.sch | 92 ++++++++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'rev03-KiCad/rev02_19.sch') diff --git a/rev03-KiCad/rev02_19.sch b/rev03-KiCad/rev02_19.sch index b76308c..0bd510a 100644 --- a/rev03-KiCad/rev02_19.sch +++ b/rev03-KiCad/rev02_19.sch @@ -306,167 +306,167 @@ Wire Wire Line 8500 6600 8400 6600 Wire Wire Line 3100 8100 1900 8100 -Text Label 2100 8100 0 48 ~ +Text GLabel 3100 8100 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_0 Wire Wire Line 3100 8200 1900 8200 -Text Label 2100 8200 0 48 ~ +Text GLabel 3100 8200 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_1 Wire Wire Line 3100 5200 1900 5200 -Text Label 2100 5200 0 48 ~ +Text GLabel 3100 5200 2 48 UnSpc ~ 0 FPGA_IRQ_N_0 Wire Wire Line 3100 5300 1900 5300 -Text Label 2100 5300 0 48 ~ +Text GLabel 3100 5300 2 48 UnSpc ~ 0 FPGA_IRQ_N_1 Wire Wire Line 3100 5400 1900 5400 -Text Label 2100 5400 0 48 ~ +Text GLabel 3100 5400 2 48 UnSpc ~ 0 FPGA_IRQ_N_2 Wire Wire Line 3100 5500 1900 5500 -Text Label 2100 5500 0 48 ~ +Text GLabel 3100 5500 2 48 UnSpc ~ 0 FPGA_IRQ_N_3 Wire Wire Line 3100 5600 1900 5600 -Text Label 2100 5800 0 48 ~ +Text GLabel 3100 5800 2 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 8500 5000 7600 5000 -Text Label 7600 5000 0 48 ~ +Text GLabel 7600 5000 0 48 BiDi ~ 0 FPGA_GPIO_A_0 Wire Wire Line 3100 5700 1900 5700 -Text Label 2100 5700 0 48 ~ +Text GLabel 3100 5700 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 10000 5000 9100 5000 -Text Label 9300 5000 0 48 ~ +Text GLabel 10000 5000 2 48 BiDi ~ 0 FPGA_GPIO_A_1 Wire Wire Line 3100 5800 1900 5800 -Text Label 2100 6900 0 48 ~ +Text GLabel 3100 6900 2 48 BiDi ~ 0 FPGA_GPIO_A_2 Wire Wire Line 8500 5100 7600 5100 -Text Label 7600 5100 0 48 ~ +Text GLabel 7600 5100 0 48 BiDi ~ 0 FPGA_GPIO_A_2 -Text Label 2100 7000 0 48 ~ +Text GLabel 3100 7000 2 48 BiDi ~ 0 FPGA_GPIO_A_3 Wire Wire Line 10000 5100 9100 5100 -Text Label 9300 5100 0 48 ~ +Text GLabel 10000 5100 2 48 BiDi ~ 0 FPGA_GPIO_A_3 -Text Label 2100 6500 0 48 ~ +Text GLabel 3100 6500 2 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 8500 5300 7600 5300 -Text Label 7600 5300 0 48 ~ +Text GLabel 7600 5300 0 48 BiDi ~ 0 FPGA_GPIO_A_4 Wire Wire Line 3100 6100 1900 6100 -Text Label 2100 6600 0 48 ~ +Text GLabel 3100 6600 2 48 BiDi ~ 0 FPGA_GPIO_A_5 Wire Wire Line 10000 5300 9100 5300 -Text Label 9300 5300 0 48 ~ +Text GLabel 10000 5300 2 48 BiDi ~ 0 FPGA_GPIO_A_5 -Text Label 2110 6700 0 48 ~ +Text GLabel 3100 6700 2 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 8500 5400 7600 5400 -Text Label 7600 5400 0 48 ~ +Text GLabel 7600 5400 0 48 BiDi ~ 0 FPGA_GPIO_A_6 Wire Wire Line 3100 6300 1900 6300 -Text Label 2100 6300 0 48 ~ +Text GLabel 3100 6300 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 10000 5400 9100 5400 -Text Label 9300 5400 0 48 ~ +Text GLabel 10000 5400 2 48 BiDi ~ 0 FPGA_GPIO_A_7 Wire Wire Line 3100 6400 1900 6400 -Text Label 2110 6800 0 48 ~ +Text GLabel 3100 6800 2 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 8500 6900 7600 6900 -Text Label 7600 6900 0 48 ~ +Text GLabel 7600 6900 0 48 BiDi ~ 0 FPGA_GPIO_B_0 Wire Wire Line 3100 6500 1900 6500 -Text Label 2100 5600 0 48 ~ +Text GLabel 3100 5600 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 10000 6900 9100 6900 -Text Label 9300 6900 0 48 ~ +Text GLabel 10000 6900 2 48 BiDi ~ 0 FPGA_GPIO_B_1 Wire Wire Line 3100 6600 1900 6600 -Text Label 2100 6400 0 48 ~ +Text GLabel 3100 6400 2 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 8500 7000 7600 7000 -Text Label 7600 7000 0 48 ~ +Text GLabel 7600 7000 0 48 BiDi ~ 0 FPGA_GPIO_B_2 Wire Wire Line 3100 6700 1900 6700 -Text Label 2110 6100 0 48 ~ +Text GLabel 3100 6100 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 10000 7000 9100 7000 -Text Label 9300 7000 0 48 ~ +Text GLabel 10000 7000 2 48 BiDi ~ 0 FPGA_GPIO_B_3 Wire Wire Line 3100 6800 1900 6800 -Text Label 2100 7500 0 48 ~ +Text GLabel 3100 7500 2 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 8500 7200 7600 7200 -Text Label 7600 7200 0 48 ~ +Text GLabel 7600 7200 0 48 BiDi ~ 0 FPGA_GPIO_B_4 Wire Wire Line 3100 6900 1900 6900 -Text Label 2100 9200 0 48 ~ +Text GLabel 3100 9200 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 10000 7200 9100 7200 -Text Label 9300 7200 0 48 ~ +Text GLabel 10000 7200 2 48 BiDi ~ 0 FPGA_GPIO_B_5 Wire Wire Line 3100 7000 1900 7000 -Text Label 2100 8800 0 48 ~ +Text GLabel 3100 8800 2 48 BiDi ~ 0 FPGA_GPIO_B_6 Wire Wire Line 8500 7300 7600 7300 -Text Label 7600 7300 0 48 ~ +Text GLabel 7600 7300 0 48 BiDi ~ 0 FPGA_GPIO_B_6 -Text Label 2100 8900 0 48 ~ +Text GLabel 3100 8900 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 10000 7300 9100 7300 -Text Label 9300 7300 0 48 ~ +Text GLabel 10000 7300 2 48 BiDi ~ 0 FPGA_GPIO_B_7 Wire Wire Line 3100 7300 1900 7300 -Text Label 2100 7300 0 48 ~ +Text GLabel 3100 7300 2 48 UnSpc ~ 0 FPGA_GCLK Wire Wire Line 7890 8700 7300 8700 -Text Label 7300 8700 0 48 ~ +Text GLabel 7300 8700 0 48 Input ~ 0 FPGA_GPIO_LED_2 Wire Wire Line 8200 8600 7300 8600 -Text Label 7300 8600 0 48 ~ +Text GLabel 7300 8600 0 48 Input ~ 0 FPGA_GPIO_LED_3 Wire Wire Line 7890 8900 7300 8900 -Text Label 7300 8900 0 48 ~ +Text GLabel 7300 8900 0 48 Input ~ 0 FPGA_GPIO_LED_0 Wire Wire Line 8200 8800 7300 8800 -Text Label 7300 8800 0 48 ~ +Text GLabel 7300 8800 0 48 Input ~ 0 FPGA_GPIO_LED_1 Wire Wire Line 8900 8900 8290 8900 @@ -478,15 +478,15 @@ Wire Wire Line 8700 8600 8600 8600 Wire Wire Line 3100 7200 1900 7200 -Text Label 2100 7200 0 48 ~ +Text GLabel 3100 7200 2 48 Output ~ 0 FPGA_ENTROPY_DISABLE Wire Wire Line 3100 8300 1900 8300 -Text Label 2100 8300 0 48 ~ +Text GLabel 3100 8300 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_2 Wire Wire Line 3100 8400 1900 8400 -Text Label 2100 8400 0 48 ~ +Text GLabel 3100 8400 2 48 UnSpc ~ 0 AVR_GPIO_FPGA_3 Wire Wire Line 3100 7500 1900 7500 -- cgit v1.2.3