From b5fb3c639793a7f3fb9cbc1bc252ab7375f6b05f Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Mon, 23 Apr 2018 17:14:24 +0200 Subject: update KiCAD Gerber files --- rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr | 42819 +++------------------ 1 file changed, 5350 insertions(+), 37469 deletions(-) (limited to 'rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr') diff --git a/rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr b/rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr index e601df5..c5c35fc 100644 --- a/rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr +++ b/rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr @@ -1,176 +1,67 @@ -%TF.GenerationSoftware,KiCad,Pcbnew,no-vcs-found-e46fdb0~60~ubuntu17.04.1*% -%TF.CreationDate,2017-09-26T11:00:32+02:00*% -%TF.ProjectId,Cryptech Alpha,437279707465636820416C7068612E6B,rev?*% -%TF.SameCoordinates,Original*% -%TF.FileFunction,Copper,L8,Bot,Signal*% -%TF.FilePolarity,Positive*% +G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.0-rc2-dev-unknown-9f5316e~63~ubuntu17.10.1* +G04 #@! TF.CreationDate,2018-04-23T17:13:08+02:00* +G04 #@! TF.ProjectId,Cryptech Alpha,437279707465636820416C7068612E6B,rev?* +G04 #@! TF.SameCoordinates,Original* +G04 #@! TF.FileFunction,Copper,L8,Bot,Signal* +G04 #@! TF.FilePolarity,Positive* %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW no-vcs-found-e46fdb0~60~ubuntu17.04.1) date Tue Sep 26 11:00:32 2017* +G04 Created by KiCad (PCBNEW 5.0.0-rc2-dev-unknown-9f5316e~63~ubuntu17.10.1) date Mon Apr 23 17:13:08 2018* %MOMM*% %LPD*% G01* G04 APERTURE LIST* -%TA.AperFunction,NonConductor*% %ADD10C,0.100000*% -%TD*% -%TA.AperFunction,ComponentPad*% %ADD11C,1.500000*% -%TD*% -%TA.AperFunction,ComponentPad*% %ADD12R,1.500000X1.500000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD13R,1.600000X2.600000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD14R,0.450000X0.600000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD15R,2.400000X2.600000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD16R,0.800000X0.800000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD17R,1.200000X1.000000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD18R,1.000000X1.200000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD19R,0.600000X0.450000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD20R,2.600000X1.600000*% -%TD*% -%TA.AperFunction,WasherPad*% %ADD21C,1.016000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD22R,1.200000X0.800000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD23R,1.400000X1.800000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD24R,1.800000X1.400000*% -%TD*% -%TA.AperFunction,ComponentPad*% %ADD25O,2.000000X4.500000*% -%TD*% -%TA.AperFunction,ComponentPad*% %ADD26O,4.500000X2.000000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD27R,1.397000X1.193800*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD28R,1.498600X1.701800*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD29R,1.016000X3.302000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD30R,3.302000X1.016000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD31R,2.616200X1.016000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD32R,1.016000X2.616200*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD33R,0.800000X1.200000*% -%TD*% -%TA.AperFunction,BGAPad,CuDef*% %ADD34C,1.270000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD35R,2.413000X0.863600*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD36R,13.385800X9.144000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD37R,1.100000X0.650000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD38O,1.100000X0.650000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD39O,0.300000X1.200000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD40O,1.200000X0.300000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD41R,0.600000X1.550000*% -%TD*% -%TA.AperFunction,BGAPad,CuDef*% %ADD42C,0.450000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD43O,2.600000X1.940000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD44O,0.609600X0.254000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD45O,0.254000X0.609600*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD46O,2.350000X5.350000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% %ADD47O,2.500000X1.300000*% -%TD*% -%TA.AperFunction,BGAPad,CuDef*% %ADD48C,1.000000*% -%TD*% -%TA.AperFunction,ViaPad*% %ADD49C,0.500000*% -%TD*% -%TA.AperFunction,ViaPad*% -%ADD50C,1.000000*% -%TD*% -%TA.AperFunction,ViaPad*% -%ADD51C,0.600000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD52C,0.150000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD53C,0.300000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD54C,0.500000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD55C,0.164000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD56C,0.200000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD57C,0.254000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD58C,1.000000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD59C,0.600000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD60C,0.250000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD61C,0.400000*% -%TD*% -%TA.AperFunction,Conductor*% -%ADD62C,0.050000*% -%TD*% -%ADD63C,0.050000*% +%ADD50C,0.600000*% +%ADD51C,0.150000*% +%ADD52C,0.300000*% +%ADD53C,0.254000*% +%ADD54C,1.000000*% +%ADD55C,0.600000*% +%ADD56C,0.500000*% +%ADD57C,0.200000*% +%ADD58C,0.164000*% +%ADD59C,0.250000*% +%ADD60C,0.400000*% G04 APERTURE END LIST* D10* X96850952Y42298761D02* @@ -284,1106 +175,372 @@ X96850952Y61288285D01* X96971904Y61046380D01* X97092857Y60925428D01* D11* -%TO.P,JP5,3*% -%TO.N,AVR_GPIO_1*% X36580000Y-6000000D03* -%TO.P,JP5,10*% -%TO.N,GND*% X54360000Y-6000000D03* -%TO.P,JP5,9*% -%TO.N,AVR_GPIO_7*% X51820000Y-6000000D03* -%TO.P,JP5,8*% -%TO.N,AVR_GPIO_6*% X49280000Y-6000000D03* -%TO.P,JP5,7*% -%TO.N,AVR_GPIO_5*% X46740000Y-6000000D03* -%TO.P,JP5,6*% -%TO.N,AVR_GPIO_4*% X44200000Y-6000000D03* -%TO.P,JP5,5*% -%TO.N,AVR_GPIO_3*% X41660000Y-6000000D03* -%TO.P,JP5,4*% -%TO.N,AVR_GPIO_2*% X39120000Y-6000000D03* -%TO.P,JP5,2*% -%TO.N,AVR_GPIO_0*% X34040000Y-6000000D03* D12* -%TO.P,JP5,1*% -%TO.N,VCCO_3V3*% X31500000Y-6000000D03* -%TD*% -%TO.P,JP6,1*% -%TO.N,GND*% X84160740Y30530000D03* D11* -%TO.P,JP6,2*% -%TO.N,MKM_AVR_MISO*% X84160740Y33070000D03* -%TD*% D13* -%TO.P,C1,2*% -%TO.N,GND*% X22963000Y99085400D03* -%TO.P,C1,1*% -%TO.N,PWR_18V*% X19963000Y99085400D03* -%TD*% -%TO.P,C2,1*% -%TO.N,PWR_18V*% X19963000Y94068900D03* -%TO.P,C2,2*% -%TO.N,GND*% X22963000Y94068900D03* -%TD*% -%TO.P,C3,2*% -%TO.N,GND*% X22963000Y89052400D03* -%TO.P,C3,1*% -%TO.N,PWR_18V*% X19963000Y89052400D03* -%TD*% D14* -%TO.P,C4,1*% -%TO.N,PWR_18V*% X25600000Y84700000D03* -%TO.P,C4,2*% -%TO.N,GND*% X26600000Y84700000D03* -%TD*% -%TO.P,C5,2*% -%TO.N,GND*% X26050000Y75725000D03* -%TO.P,C5,1*% -%TO.N,NetC5_1*% X25050000Y75725000D03* -%TD*% -%TO.P,C6,1*% -%TO.N,VCC_5V0*% X25077800Y71831200D03* -%TO.P,C6,2*% -%TO.N,GND*% X26077800Y71831200D03* -%TD*% D13* -%TO.P,C8,1*% -%TO.N,VCC_5V0*% X16790800Y67335400D03* -%TO.P,C8,2*% -%TO.N,GND*% X13790800Y67335400D03* -%TD*% D15* -%TO.P,C9,1*% -%TO.N,VCC_5V0*% X13714800Y54584600D03* -%TO.P,C9,2*% -%TO.N,GND*% X7214800Y54584600D03* -%TD*% -%TO.P,C10,2*% -%TO.N,GND*% X7214800Y61061600D03* -%TO.P,C10,1*% -%TO.N,VCC_5V0*% X13714800Y61061600D03* -%TD*% D14* -%TO.P,C14,2*% -%TO.N,NOISE_IN*% X89492200Y96215200D03* -%TO.P,C14,1*% -%TO.N,GND*% X90492200Y96215200D03* -%TD*% -%TO.P,C15,1*% -%TO.N,RAW_NOISE*% X89984200Y81686400D03* -%TO.P,C15,2*% -%TO.N,NetC15_2*% X88984200Y81686400D03* -%TD*% -%TO.P,C16,2*% -%TO.N,VCCO_3V3*% X76843000Y88544400D03* -%TO.P,C16,1*% -%TO.N,GND*% X77843000Y88544400D03* -%TD*% -%TO.P,C17,1*% -%TO.N,GND*% X28425000Y32050000D03* -%TO.P,C17,2*% -%TO.N,NetC17_2*% X29425000Y32050000D03* -%TD*% -%TO.P,C18,2*% -%TO.N,OSC_OUT*% X27675000Y38550000D03* -%TO.P,C18,1*% -%TO.N,GND*% X28675000Y38550000D03* -%TD*% D16* -%TO.P,C21,2*% -%TO.N,GND*% X48426600Y14249400D03* -%TO.P,C21,1*% -%TO.N,VCCO_3V3*% X47026600Y14249400D03* -%TD*% -%TO.P,C22,1*% -%TO.N,GND*% X55767200Y51511200D03* -%TO.P,C22,2*% -%TO.N,VCAP1*% X54367200Y51511200D03* -%TD*% -%TO.P,C23,2*% -%TO.N,VCAP1*% X54367200Y49682400D03* -%TO.P,C23,1*% -%TO.N,GND*% X55767200Y49682400D03* -%TD*% -%TO.P,C24,1*% -%TO.N,GND*% X65963800Y23684000D03* -%TO.P,C24,2*% -%TO.N,VCAP2*% X65963800Y25084000D03* -%TD*% -%TO.P,C25,2*% -%TO.N,VCAP2*% X67792600Y25084000D03* -%TO.P,C25,1*% -%TO.N,GND*% X67792600Y23684000D03* -%TD*% D17* -%TO.P,C26,2*% -%TO.N,GND*% X29718000Y25568400D03* -%TO.P,C26,1*% -%TO.N,VCCO_3V3*% X29718000Y27568400D03* -%TD*% D18* -%TO.P,C27,1*% -%TO.N,VCCO_3V3*% X46694600Y51333400D03* -%TO.P,C27,2*% -%TO.N,GND*% X44694600Y51333400D03* -%TD*% D14* -%TO.P,C28,1*% -%TO.N,VCCO_3V3*% X51147600Y49352200D03* -%TO.P,C28,2*% -%TO.N,GND*% X50147600Y49352200D03* -%TD*% D19* -%TO.P,C29,2*% -%TO.N,GND*% X65430400Y35161600D03* -%TO.P,C29,1*% -%TO.N,VCCO_3V3*% X65430400Y36161600D03* -%TD*% -%TO.P,C30,1*% -%TO.N,VCCO_3V3*% X57353200Y49284000D03* -%TO.P,C30,2*% -%TO.N,GND*% X57353200Y50284000D03* -%TD*% D14* -%TO.P,C31,2*% -%TO.N,GND*% X61841000Y15951200D03* -%TO.P,C31,1*% -%TO.N,VCCO_3V3*% X60841000Y15951200D03* -%TD*% D19* -%TO.P,C32,1*% -%TO.N,VCCO_3V3*% X31927800Y27119200D03* -%TO.P,C32,2*% -%TO.N,GND*% X31927800Y26119200D03* -%TD*% -%TO.P,C33,2*% -%TO.N,GND*% X30530800Y41978200D03* -%TO.P,C33,1*% -%TO.N,VCCO_3V3*% X30530800Y40978200D03* -%TD*% -%TO.P,C34,1*% -%TO.N,VCCO_3V3*% X60934600Y49284000D03* -%TO.P,C34,2*% -%TO.N,GND*% X60934600Y50284000D03* -%TD*% -%TO.P,C36,1*% -%TO.N,VCCO_3V3*% X65430400Y29243400D03* -%TO.P,C36,2*% -%TO.N,GND*% X65430400Y30243400D03* -%TD*% D14* -%TO.P,C38,1*% -%TO.N,VCCO_3V3*% X47226600Y15951200D03* -%TO.P,C38,2*% -%TO.N,GND*% X48226600Y15951200D03* -%TD*% -%TO.P,C39,2*% -%TO.N,GND*% X55186200Y15951200D03* -%TO.P,C39,1*% -%TO.N,VCCO_3V3*% X54186200Y15951200D03* -%TD*% D19* -%TO.P,C40,1*% -%TO.N,VCCO_3V3*% X31927800Y45635800D03* -%TO.P,C40,2*% -%TO.N,GND*% X31927800Y44635800D03* -%TD*% -%TO.P,C41,2*% -%TO.N,GND*% X31927800Y41978200D03* -%TO.P,C41,1*% -%TO.N,VCCO_3V3*% X31927800Y40978200D03* -%TD*% D14* -%TO.P,C42,1*% -%TO.N,VCCO_3V3*% X65794000Y21971000D03* -%TO.P,C42,2*% -%TO.N,GND*% X66794000Y21971000D03* -%TD*% -%TO.P,C43,2*% -%TO.N,GND*% X39717600Y49352200D03* -%TO.P,C43,1*% -%TO.N,VCCO_3V3*% X38717600Y49352200D03* -%TD*% -%TO.P,C44,1*% -%TO.N,VCCO_3V3*% X46143800Y49352200D03* -%TO.P,C44,2*% -%TO.N,GND*% X45143800Y49352200D03* -%TD*% D19* -%TO.P,C45,2*% -%TO.N,GND*% X65430400Y41114600D03* -%TO.P,C45,1*% -%TO.N,VCCO_3V3*% X65430400Y40114600D03* -%TD*% -%TO.P,C46,1*% -%TO.N,VCCO_3V3*% X31927800Y32377000D03* -%TO.P,C46,2*% -%TO.N,GND*% X31927800Y31377000D03* -%TD*% -%TO.P,C58,1*% -%TO.N,VCCO_3V3*% X72822200Y40392400D03* -%TO.P,C58,2*% -%TO.N,GND*% X72822200Y41392400D03* -%TD*% -%TO.P,C59,2*% -%TO.N,GND*% X72847200Y38182600D03* -%TO.P,C59,1*% -%TO.N,VCCO_3V3*% X72847200Y39182600D03* -%TD*% -%TO.P,C60,1*% -%TO.N,VCCO_3V3*% X72847200Y60456800D03* -%TO.P,C60,2*% -%TO.N,GND*% X72847200Y61456800D03* -%TD*% -%TO.P,C61,2*% -%TO.N,GND*% X88722200Y59166000D03* -%TO.P,C61,1*% -%TO.N,VCCO_3V3*% X88722200Y58166000D03* -%TD*% -%TO.P,C62,1*% -%TO.N,VCCO_3V3*% X72847200Y53128800D03* -%TO.P,C62,2*% -%TO.N,GND*% X72847200Y52128800D03* -%TD*% -%TO.P,C63,2*% -%TO.N,GND*% X88722200Y40648000D03* -%TO.P,C63,1*% -%TO.N,VCCO_3V3*% X88722200Y41648000D03* -%TD*% -%TO.P,C64,1*% -%TO.N,VCCO_3V3*% X72847200Y59097800D03* -%TO.P,C64,2*% -%TO.N,GND*% X72847200Y58097800D03* -%TD*% -%TO.P,C65,2*% -%TO.N,GND*% X88722200Y56045800D03* -%TO.P,C65,1*% -%TO.N,VCCO_3V3*% X88722200Y55045800D03* -%TD*% -%TO.P,C66,1*% -%TO.N,VCCO_3V3*% X72847200Y46042200D03* -%TO.P,C66,2*% -%TO.N,GND*% X72847200Y45042200D03* -%TD*% -%TO.P,C67,2*% -%TO.N,GND*% X88722200Y45987400D03* -%TO.P,C67,1*% -%TO.N,VCCO_3V3*% X88722200Y44987400D03* -%TD*% -%TO.P,C68,1*% -%TO.N,VCCO_3V3*% X72847200Y56151400D03* -%TO.P,C68,2*% -%TO.N,GND*% X72847200Y55151400D03* -%TD*% D18* -%TO.P,C72,2*% -%TO.N,GND*% X20775860Y5961430D03* -%TO.P,C72,1*% -%TO.N,FT_VREGIN*% X18775860Y5961430D03* -%TD*% D14* -%TO.P,C73,1*% -%TO.N,FT_VREGIN*% X12872020Y7066020D03* -%TO.P,C73,2*% -%TO.N,GND*% X11872020Y7066020D03* -%TD*% D17* -%TO.P,C87,2*% -%TO.N,GND*% X78403810Y18070950D03* -%TO.P,C87,1*% -%TO.N,FT_MGMT_VREGIN*% X78403810Y16070950D03* -%TD*% D19* -%TO.P,C88,2*% -%TO.N,GND*% X82508380Y17834860D03* -%TO.P,C88,1*% -%TO.N,FT_MGMT_VREGIN*% X82508380Y18834860D03* -%TD*% -%TO.P,C105,1*% -%TO.N,VCCO_3V3*% X31500000Y-8000000D03* -%TO.P,C105,2*% -%TO.N,GND*% X31500000Y-9000000D03* -%TD*% -%TO.P,C107,1*% -%TO.N,3V3_BATT*% X76682600Y27474800D03* -%TO.P,C107,2*% -%TO.N,GND*% X76682600Y28474800D03* -%TD*% -%TO.P,C108,2*% -%TO.N,GND*% X31484200Y-1500000D03* -%TO.P,C108,1*% -%TO.N,VCCO_3V3*% X31484200Y-500000D03* -%TD*% D14* -%TO.P,C111,1*% -%TO.N,VCCO_3V3*% X66700400Y88442800D03* -%TO.P,C111,2*% -%TO.N,GND*% X65700400Y88442800D03* -%TD*% D20* -%TO.P,C113,2*% -%TO.N,GND*% X40055800Y74118600D03* -%TO.P,C113,1*% -%TO.N,VCC_5V0*% X40055800Y71118600D03* -%TD*% -%TO.P,C114,1*% -%TO.N,VCC_5V0*% X6400800Y46432600D03* -%TO.P,C114,2*% -%TO.N,GND*% X6400800Y43432600D03* -%TD*% D19* -%TO.P,C115,1*% -%TO.N,NetC115_1*% X32181800Y75344400D03* -%TO.P,C115,2*% -%TO.N,GND*% X32181800Y76344400D03* -%TD*% -%TO.P,C116,2*% -%TO.N,GND*% X13950000Y41125000D03* -%TO.P,C116,1*% -%TO.N,NetC116_1*% X13950000Y42125000D03* -%TD*% -%TO.P,C117,1*% -%TO.N,NetC117_1*% X32181800Y80891000D03* -%TO.P,C117,2*% -%TO.N,NetC117_2*% X32181800Y79891000D03* -%TD*% -%TO.P,C118,2*% -%TO.N,NetC118_2*% X13975000Y37850000D03* -%TO.P,C118,1*% -%TO.N,NetC118_1*% X13975000Y36850000D03* -%TD*% D20* -%TO.P,C119,2*% -%TO.N,GND*% X40055800Y77900400D03* -%TO.P,C119,1*% -%TO.N,NetC117_1*% X40055800Y80900400D03* -%TD*% -%TO.P,C120,1*% -%TO.N,NetC118_1*% X6400800Y37082600D03* -%TO.P,C120,2*% -%TO.N,GND*% X6400800Y40082600D03* -%TD*% D19* -%TO.P,C121,1*% -%TO.N,VCCO_3V3*% X71075000Y97200000D03* -%TO.P,C121,2*% -%TO.N,GND*% X71075000Y98200000D03* -%TD*% D13* -%TO.P,C205,1*% -%TO.N,VCC_5V0*% X20547200Y50647600D03* -%TO.P,C205,2*% -%TO.N,GND*% X23547200Y50647600D03* -%TD*% -%TO.P,C206,2*% -%TO.N,GND*% X23547200Y46278800D03* -%TO.P,C206,1*% -%TO.N,VCC_5V0*% X20547200Y46278800D03* -%TD*% D14* -%TO.P,C207,1*% -%TO.N,NetC207_1*% X24985600Y62890400D03* -%TO.P,C207,2*% -%TO.N,GND*% X23985600Y62890400D03* -%TD*% -%TO.P,C208,2*% -%TO.N,NetC208_2*% X26424000Y62890400D03* -%TO.P,C208,1*% -%TO.N,NetC208_1*% X27424000Y62890400D03* -%TD*% D20* -%TO.P,C209,1*% -%TO.N,NetC208_1*% X34696400Y56846600D03* -%TO.P,C209,2*% -%TO.N,GND*% X34696400Y53846600D03* -%TD*% -%TO.P,C210,2*% -%TO.N,GND*% X34747200Y63907800D03* -%TO.P,C210,1*% -%TO.N,NetC208_1*% X34747200Y60907800D03* -%TD*% D21* -%TO.P,CN1,*% -%TO.N,*% X67209800Y-13884000D03* X62800000Y-13884000D03* -%TD*% -%TO.P,CN2,*% -%TO.N,*% X82800000Y-13884000D03* X87209800Y-13884000D03* -%TD*% D22* -%TO.P,D1,3*% -%TO.N,AMPLIFIED*% X81754800Y89179400D03* -%TO.P,D1,2*% -%TO.N,N/C*% X83954800Y88229400D03* -%TO.P,D1,1*% -%TO.N,NetC15_2*% X83954800Y90129400D03* -%TD*% D23* -%TO.P,FB5,2*% -%TO.N,FPGA_VCCAUX_1V8*% X42852800Y84277200D03* -%TO.P,FB5,1*% -%TO.N,NetC117_1*% X40052800Y84277200D03* -%TD*% -%TO.P,FB6,1*% -%TO.N,NetC118_1*% X6397800Y33147000D03* -%TO.P,FB6,2*% -%TO.N,VCCO_3V3*% X9197800Y33147000D03* -%TD*% D24* -%TO.P,FB7,2*% -%TO.N,FPGA_VCCINT_1V0*% X39624000Y59616800D03* -%TO.P,FB7,1*% -%TO.N,NetC208_1*% X39624000Y56816800D03* -%TD*% D11* -%TO.P,J1,6*% -%TO.N,N/C*% X29133790Y20421600D03* -%TO.P,J1,5*% -%TO.N,NRST*% X26593790Y20421600D03* -%TO.P,J1,4*% -%TO.N,SWDIO*% X24053790Y20421600D03* -%TO.P,J1,3*% -%TO.N,GND*% X21513790Y20421600D03* -%TO.P,J1,2*% -%TO.N,SWDCLK*% X18973790Y20421600D03* D12* -%TO.P,J1,1*% -%TO.N,VCCO_3V3*% X16433790Y20421600D03* -%TD*% -%TO.P,J2,1*% -%TO.N,GND*% X38506390Y11252200D03* D11* -%TO.P,J2,2*% -%TO.N,FT_VREGIN*% X38506390Y13792200D03* -%TO.P,J2,3*% -%TO.N,USB_P*% X41046390Y11252200D03* -%TO.P,J2,4*% -%TO.N,USB_N*% X41046390Y13792200D03* -%TO.P,J2,5*% -%TO.N,FT_RXD1*% X43586390Y11252200D03* -%TO.P,J2,6*% -%TO.N,FT_TXD1*% X43586390Y13792200D03* -%TD*% -%TO.P,J3,6*% -%TO.N,FT_MGMT_TXD1*% X77444590Y13792200D03* -%TO.P,J3,5*% -%TO.N,FT_MGMT_RXD1*% X77444590Y11252200D03* -%TO.P,J3,4*% -%TO.N,USB_MGMT_N*% X74904590Y13792200D03* -%TO.P,J3,3*% -%TO.N,USB_MGMT_P*% X74904590Y11252200D03* -%TO.P,J3,2*% -%TO.N,FT_MGMT_VREGIN*% X72364590Y13792200D03* D12* -%TO.P,J3,1*% -%TO.N,GND*% X72364590Y11252200D03* -%TD*% D25* -%TO.P,JP1,3*% -%TO.N,GND*% X24800000Y-7800000D03* D26* -%TO.P,JP1,2*% X20000000Y-10600000D03* -%TO.P,JP1,1*% -%TO.N,PWR_18V*% X20000000Y-4800000D03* -%TD*% D11* -%TO.P,JP2,2*% -%TO.N,NetJP2_2*% X65916800Y91744800D03* D12* -%TO.P,JP2,1*% -%TO.N,15V_LDO_ENABLE*% X63376800Y91744800D03* -%TD*% -%TO.P,JP3,1*% -%TO.N,MKM_AVR_MISO*% X87847000Y33705800D03* D11* -%TO.P,JP3,2*% -%TO.N,3V3_BATT*% X90387000Y33705800D03* -%TO.P,JP3,3*% -%TO.N,MKM_AVR_SCK*% X87847000Y31165800D03* -%TO.P,JP3,4*% -%TO.N,MKM_AVR_MOSI*% X90387000Y31165800D03* -%TO.P,JP3,5*% -%TO.N,AVR_RESET*% X87847000Y28625800D03* -%TO.P,JP3,6*% -%TO.N,GND*% X90387000Y28625800D03* -%TD*% -%TO.P,JP4,3*% -%TO.N,GND*% X91219330Y-1500000D03* -%TO.P,JP4,2*% -%TO.N,3V3_BATT*% X88679330Y-1500000D03* D12* -%TO.P,JP4,1*% -%TO.N,VCCO_3V3*% X86139330Y-1500000D03* -%TD*% -%TO.P,JP7,1*% -%TO.N,FPGA_CFG_CTRL_ARM_ENA*% X16980000Y32015000D03* D11* -%TO.P,JP7,2*% -%TO.N,SPI_A_TRISTATE*% X19520000Y32015000D03* -%TO.P,JP7,3*% -%TO.N,FPGA_CFG_CTRL_FPGA_DIS*% X16980000Y29475000D03* -%TO.P,JP7,4*% -%TO.N,SPI_B_TRISTATE*% X19520000Y29475000D03* -%TO.P,JP7,5*% -%TO.N,FPGA_PROM_W_N*% X16980000Y26935000D03* -%TO.P,JP7,6*% -%TO.N,VCCO_3V3*% X19520000Y26935000D03* -%TD*% D22* -%TO.P,Q2,1*% -%TO.N,NOISE_OUT*% X89273200Y91836200D03* -%TO.P,Q2,2*% -%TO.N,NOISE_IN*% X89273200Y93736200D03* -%TO.P,Q2,3*% -%TO.N,N/C*% X91473200Y92786200D03* -%TD*% D27* -%TO.P,Q3,4*% -%TO.N,GND*% X29417600Y35838600D03* -%TO.P,Q3,3*% -%TO.N,OSC_OUT*% X27207800Y35838600D03* -%TO.P,Q3,2*% -%TO.N,GND*% X27207800Y34136800D03* -%TO.P,Q3,1*% -%TO.N,NetC17_2*% X29417600Y34136800D03* -%TD*% D28* -%TO.P,Q5,4*% -%TO.N,VCCO_3V3*% X66878200Y85961400D03* -%TO.P,Q5,3*% -%TO.N,NetQ5_3*% X66878200Y83413600D03* -%TO.P,Q5,1*% -%TO.N,NetQ5_1*% X69100600Y85961400D03* -%TO.P,Q5,2*% -%TO.N,GND*% X69100600Y83413600D03* -%TD*% D19* -%TO.P,R4,1*% -%TO.N,FPGA_GCLK*% X64490600Y82431000D03* -%TO.P,R4,2*% -%TO.N,NetQ5_3*% X64490600Y83431000D03* -%TD*% -%TO.P,R7,2*% -%TO.N,15V_LDO_ENABLE*% X71000000Y90000000D03* -%TO.P,R7,1*% -%TO.N,PWR_18V*% X71000000Y89000000D03* -%TD*% D14* -%TO.P,R8,1*% -%TO.N,NetR8_1*% X26077800Y73177400D03* -%TO.P,R8,2*% -%TO.N,VCC_5V0*% X25077800Y73177400D03* -%TD*% D19* -%TO.P,R9,2*% -%TO.N,NetR8_1*% X28194000Y73118600D03* -%TO.P,R9,1*% -%TO.N,GND*% X28194000Y72118600D03* -%TD*% -%TO.P,R10,1*% -%TO.N,RAW_NOISE*% X87096600Y92743400D03* -%TO.P,R10,2*% -%TO.N,NOISE_IN*% X87096600Y93743400D03* -%TD*% D14* -%TO.P,R11,2*% -%TO.N,RAW_NOISE*% X90482800Y84632800D03* -%TO.P,R11,1*% -%TO.N,15V_STABLE*% X91482800Y84632800D03* -%TD*% -%TO.P,R12,1*% -%TO.N,NetC15_2*% X85158200Y86106000D03* -%TO.P,R12,2*% -%TO.N,AMPLIFIED*% X84158200Y86106000D03* -%TD*% D19* -%TO.P,R13,2*% -%TO.N,VCCO_3V3*% X80695800Y81389600D03* -%TO.P,R13,1*% -%TO.N,AMPLIFIED*% X80695800Y82389600D03* -%TD*% -%TO.P,R14,1*% -%TO.N,OSC_IN*% X31927800Y35171000D03* -%TO.P,R14,2*% -%TO.N,NetC17_2*% X31927800Y34171000D03* -%TD*% -%TO.P,R16,1*% -%TO.N,NetLED4_1*% X45000000Y7000000D03* -%TO.P,R16,2*% -%TO.N,ARM_LED3*% X45000000Y8000000D03* -%TD*% -%TO.P,R31,2*% -%TO.N,AVR_LED3*% X28000000Y8000000D03* -%TO.P,R31,1*% -%TO.N,NetLED12_1*% X28000000Y7000000D03* -%TD*% D14* -%TO.P,R33,2*% -%TO.N,NetR33_2*% X79646400Y25841200D03* -%TO.P,R33,1*% -%TO.N,3V3_BATT*% X78646400Y25841200D03* -%TD*% D19* -%TO.P,R34,1*% -%TO.N,MKM_CS_N*% X76675000Y33700000D03* -%TO.P,R34,2*% -%TO.N,3V3_BATT*% X76675000Y32700000D03* -%TD*% D14* -%TO.P,R49,2*% -%TO.N,VCCO_3V3*% X68080000Y88442800D03* -%TO.P,R49,1*% -%TO.N,NetQ5_1*% X69080000Y88442800D03* -%TD*% -%TO.P,R52,1*% -%TO.N,NetR52_1*% X34729800Y71805800D03* -%TO.P,R52,2*% -%TO.N,VCC_5V0*% X35729800Y71805800D03* -%TD*% D19* -%TO.P,R53,2*% -%TO.N,NetR53_2*% X30810200Y75344400D03* -%TO.P,R53,1*% -%TO.N,GND*% X30810200Y76344400D03* -%TD*% D14* -%TO.P,R54,1*% -%TO.N,NetR54_1*% X11591800Y45720000D03* -%TO.P,R54,2*% -%TO.N,VCC_5V0*% X10591800Y45720000D03* -%TD*% D19* -%TO.P,R55,2*% -%TO.N,NetR55_2*% X15519400Y42232200D03* -%TO.P,R55,1*% -%TO.N,GND*% X15519400Y41232200D03* -%TD*% -%TO.P,R56,1*% -%TO.N,NetC117_2*% X30810200Y79891000D03* -%TO.P,R56,2*% -%TO.N,NetC117_1*% X30810200Y80891000D03* -%TD*% -%TO.P,R57,2*% -%TO.N,NetC117_2*% X31546800Y78605000D03* -%TO.P,R57,1*% -%TO.N,GND*% X31546800Y77605000D03* -%TD*% -%TO.P,R58,1*% -%TO.N,NetC118_2*% X15367000Y37838000D03* -%TO.P,R58,2*% -%TO.N,NetC118_1*% X15367000Y36838000D03* -%TD*% -%TO.P,R59,2*% -%TO.N,NetC118_2*% X14732000Y39047800D03* -%TO.P,R59,1*% -%TO.N,GND*% X14732000Y40047800D03* -%TD*% D14* -%TO.P,R60,1*% -%TO.N,GND*% X36100000Y81475000D03* -%TO.P,R60,2*% -%TO.N,NetC117_1*% X37100000Y81475000D03* -%TD*% -%TO.P,R61,2*% -%TO.N,NetC118_1*% X9025000Y35864800D03* -%TO.P,R61,1*% -%TO.N,GND*% X10025000Y35864800D03* -%TD*% D19* -%TO.P,R64,1*% -%TO.N,NetLED15_1*% X81000000Y6500000D03* -%TO.P,R64,2*% -%TO.N,FPGA_GPIO_LED_1*% X81000000Y7500000D03* -%TD*% D14* -%TO.P,R66,1*% -%TO.N,NetR66_1*% X21572600Y62890400D03* -%TO.P,R66,2*% -%TO.N,VCC_5V0*% X22572600Y62890400D03* -%TD*% -%TO.P,R67,2*% -%TO.N,NetC208_1*% X29811600Y62890400D03* -%TO.P,R67,1*% -%TO.N,NetR67_1*% X28811600Y62890400D03* -%TD*% -%TO.P,R68,1*% -%TO.N,NetC208_2*% X26424000Y64566800D03* -%TO.P,R68,2*% -%TO.N,NetC208_1*% X27424000Y64566800D03* -%TD*% -%TO.P,R69,2*% -%TO.N,NetC208_2*% X24985600Y64566800D03* -%TO.P,R69,1*% -%TO.N,GND*% X23985600Y64566800D03* -%TD*% -%TO.P,R70,1*% -%TO.N,GND*% X30802200Y64566800D03* -%TO.P,R70,2*% -%TO.N,NetC208_1*% X29802200Y64566800D03* -%TD*% -%TO.P,R80,2*% -%TO.N,3V3_BATT*% X76827000Y25841200D03* -%TO.P,R80,1*% -%TO.N,MKM_CONTROL_AVR_ENA*% X75827000Y25841200D03* -%TD*% -%TO.P,R81,1*% -%TO.N,MKM_CONTROL_FPGA_DIS*% X69675000Y35150000D03* -%TO.P,R81,2*% -%TO.N,GND*% X68675000Y35150000D03* -%TD*% -%TO.P,R82,2*% -%TO.N,3V3_BATT*% X70705600Y36229800D03* -%TO.P,R82,1*% -%TO.N,AVR_PANIC*% X69705600Y36229800D03* -%TD*% D19* -%TO.P,R92,2*% -%TO.N,ARM_LED2*% X47000000Y8000000D03* -%TO.P,R92,1*% -%TO.N,NetLED1_1*% X47000000Y7000000D03* -%TD*% -%TO.P,R93,1*% -%TO.N,NetLED3_1*% X41000000Y7000000D03* -%TO.P,R93,2*% -%TO.N,ARM_LED1*% X41000000Y8000000D03* -%TD*% -%TO.P,R94,2*% -%TO.N,ARM_LED4*% X43000000Y8000000D03* -%TO.P,R94,1*% -%TO.N,NetLED2_1*% X43000000Y7000000D03* -%TD*% -%TO.P,R95,1*% -%TO.N,NetLED9_1*% X30000000Y7000000D03* -%TO.P,R95,2*% -%TO.N,AVR_LED2*% X30000000Y8000000D03* -%TD*% -%TO.P,R96,2*% -%TO.N,AVR_LED1*% X24000000Y8000000D03* -%TO.P,R96,1*% -%TO.N,NetLED11_1*% X24000000Y7000000D03* -%TD*% -%TO.P,R97,1*% -%TO.N,NetLED10_1*% X26000000Y7000000D03* -%TO.P,R97,2*% -%TO.N,AVR_LED4*% X26000000Y8000000D03* -%TD*% -%TO.P,R98,2*% -%TO.N,FPGA_GPIO_LED_2*% X79000000Y7500000D03* -%TO.P,R98,1*% -%TO.N,NetLED16_1*% X79000000Y6500000D03* -%TD*% -%TO.P,R99,1*% -%TO.N,NetLED14_1*% X77000000Y6500000D03* -%TO.P,R99,2*% -%TO.N,FPGA_GPIO_LED_3*% X77000000Y7500000D03* -%TD*% -%TO.P,R100,2*% -%TO.N,FPGA_GPIO_LED_0*% X75000000Y7500000D03* -%TO.P,R100,1*% -%TO.N,NetLED17_1*% X75000000Y6500000D03* -%TD*% D29* -%TO.P,S1,1*% -%TO.N,GND*% X94081600Y98134000D03* X73570000Y98134000D03* X73570000Y79915400D03* @@ -1403,2799 +560,1057 @@ X94081600Y92774600D03* X94081600Y85265400D03* X73570000Y85265400D03* X73570000Y92774600D03* -%TD*% D11* -%TO.P,SV1,8*% -%TO.N,GND*% X49190000Y1300000D03* D12* -%TO.P,SV1,1*% -%TO.N,VCCO_3V3*% X31410000Y1300000D03* D11* -%TO.P,SV1,2*% -%TO.N,FPGA_JTAG_TCK*% X33950000Y1300000D03* -%TO.P,SV1,3*% -%TO.N,FPGA_JTAG_TMS*% X36490000Y1300000D03* -%TO.P,SV1,4*% -%TO.N,FPGA_JTAG_TDI*% X39030000Y1300000D03* -%TO.P,SV1,5*% -%TO.N,FPGA_JTAG_TDO*% X41570000Y1300000D03* -%TO.P,SV1,6*% -%TO.N,GND*% X44110000Y1300000D03* -%TO.P,SV1,7*% X46650000Y1300000D03* -%TD*% -%TO.P,SV2,16*% -%TO.N,FPGA_GPIO_A_7*% X50692990Y96494600D03* -%TO.P,SV2,15*% -%TO.N,FPGA_GPIO_A_6*% X50692990Y99034600D03* -%TO.P,SV2,14*% -%TO.N,FPGA_GPIO_A_5*% X53232990Y96494600D03* -%TO.P,SV2,13*% -%TO.N,FPGA_GPIO_A_4*% X53232990Y99034600D03* -%TO.P,SV2,12*% -%TO.N,GND*% X55772990Y96494600D03* -%TO.P,SV2,11*% X55772990Y99034600D03* -%TO.P,SV2,10*% -%TO.N,FPGA_GPIO_A_3*% X58312990Y96494600D03* -%TO.P,SV2,9*% -%TO.N,FPGA_GPIO_A_2*% X58312990Y99034600D03* -%TO.P,SV2,8*% -%TO.N,FPGA_GPIO_A_1*% X60852990Y96494600D03* -%TO.P,SV2,7*% -%TO.N,FPGA_GPIO_A_0*% X60852990Y99034600D03* -%TO.P,SV2,6*% -%TO.N,GND*% X63392990Y96494600D03* -%TO.P,SV2,5*% X63392990Y99034600D03* -%TO.P,SV2,4*% -%TO.N,VCCO_3V3*% X65932990Y96494600D03* -%TO.P,SV2,3*% X65932990Y99034600D03* -%TO.P,SV2,2*% X68472990Y96494600D03* D12* -%TO.P,SV2,1*% X68472990Y99034600D03* -%TD*% -%TO.P,SV3,1*% -%TO.N,VCCO_3V3*% X45689190Y99034600D03* D11* -%TO.P,SV3,2*% X45689190Y96494600D03* -%TO.P,SV3,3*% X43149190Y99034600D03* -%TO.P,SV3,4*% X43149190Y96494600D03* -%TO.P,SV3,5*% -%TO.N,GND*% X40609190Y99034600D03* -%TO.P,SV3,6*% X40609190Y96494600D03* -%TO.P,SV3,7*% -%TO.N,FPGA_GPIO_B_0*% X38069190Y99034600D03* -%TO.P,SV3,8*% -%TO.N,FPGA_GPIO_B_1*% X38069190Y96494600D03* -%TO.P,SV3,9*% -%TO.N,FPGA_GPIO_B_2*% X35529190Y99034600D03* -%TO.P,SV3,10*% -%TO.N,FPGA_GPIO_B_3*% X35529190Y96494600D03* -%TO.P,SV3,11*% -%TO.N,GND*% X32989190Y99034600D03* -%TO.P,SV3,12*% X32989190Y96494600D03* -%TO.P,SV3,13*% -%TO.N,FPGA_GPIO_B_4*% X30449190Y99034600D03* -%TO.P,SV3,14*% -%TO.N,FPGA_GPIO_B_5*% X30449190Y96494600D03* -%TO.P,SV3,15*% -%TO.N,FPGA_GPIO_B_6*% X27909190Y99034600D03* -%TO.P,SV3,16*% -%TO.N,FPGA_GPIO_B_7*% X27909190Y96494600D03* -%TD*% D33* -%TO.P,T1,3*% -%TO.N,RAW_NOISE*% X90220800Y87063400D03* -%TO.P,T1,2*% -%TO.N,GND*% X91170800Y89263400D03* -%TO.P,T1,1*% -%TO.N,NOISE_OUT*% X89270800Y89263400D03* -%TD*% -%TO.P,T2,1*% -%TO.N,NetC15_2*% X85151000Y81653200D03* -%TO.P,T2,2*% -%TO.N,GND*% X83251000Y81653200D03* -%TO.P,T2,3*% -%TO.N,AMPLIFIED*% X84201000Y83853200D03* -%TD*% D34* -%TO.P,TP1,TP*% -%TO.N,RAW_NOISE*% X88315800Y85140800D03* -%TD*% -%TO.P,TP2,TP*% -%TO.N,AMPLIFIED*% X82143600Y85140800D03* -%TD*% D35* -%TO.P,U1,1*% -%TO.N,PWR_18V*% X22275800Y84632800D03* -%TO.P,U1,2*% X22275800Y83362800D03* -%TO.P,U1,3*% -%TO.N,GND*% X22275800Y82092800D03* -%TO.P,U1,4*% -%TO.N,NetR3_2*% X22275800Y80822800D03* -%TO.P,U1,5*% -%TO.N,GND*% X22275800Y79552800D03* -%TO.P,U1,6*% X22275800Y78282800D03* -%TO.P,U1,7*% -%TO.N,NetR8_1*% X22275800Y77012800D03* D36* -%TO.P,U1,TP1*% -%TO.N,GND*% X12750800Y78282800D03* D35* -%TO.P,U1,8*% -%TO.N,NetC5_1*% X22275800Y75742800D03* -%TO.P,U1,9*% -%TO.N,N/C*% X22275800Y74472800D03* -%TO.P,U1,10*% -%TO.N,VCC_5V0*% X22275800Y73202800D03* -%TO.P,U1,11*% X22275800Y71932800D03* -%TD*% D37* -%TO.P,U3,5*% -%TO.N,VCCO_3V3*% X76018400Y86090800D03* -%TO.P,U3,4*% -%TO.N,DIGITIZED_NOISE*% X76018400Y84190800D03* -%TO.P,U3,3*% -%TO.N,GND*% X78718400Y84190800D03* -%TO.P,U3,2*% -%TO.N,AMPLIFIED*% X78718400Y85140800D03* D38* -%TO.P,U3,1*% -%TO.N,N/C*% X78718400Y86090800D03* -%TD*% D39* -%TO.P,U4,208*% -%TO.N,FMC_D29*% X35941800Y17863600D03* -%TO.P,U4,207*% -%TO.N,FMC_D28*% X36441800Y17863600D03* -%TO.P,U4,206*% -%TO.N,FMC_NBL3*% X36941800Y17863600D03* -%TO.P,U4,205*% -%TO.N,FMC_NBL2*% X37441800Y17863600D03* -%TO.P,U4,204*% -%TO.N,VCCO_3V3*% X37941800Y17863600D03* -%TO.P,U4,203*% X38441800Y17863600D03* -%TO.P,U4,202*% -%TO.N,GND*% X38941800Y17863600D03* -%TO.P,U4,201*% -%TO.N,FMC_NBL1*% X39441800Y17863600D03* -%TO.P,U4,200*% -%TO.N,FMC_NBL0*% X39941800Y17863600D03* -%TO.P,U4,199*% -%TO.N,N/C*% X40441800Y17863600D03* -%TO.P,U4,198*% X40941800Y17863600D03* -%TO.P,U4,197*% -%TO.N,BOOT0*% X41441800Y17863600D03* -%TO.P,U4,196*% -%TO.N,FMC_NL*% X41941800Y17863600D03* -%TO.P,U4,195*% -%TO.N,FMC_SDNE1*% X42441800Y17863600D03* -%TO.P,U4,194*% -%TO.N,FMC_SDCKE1*% X42941800Y17863600D03* -%TO.P,U4,193*% -%TO.N,N/C*% X43441800Y17863600D03* -%TO.P,U4,192*% X43941800Y17863600D03* -%TO.P,U4,191*% -%TO.N,FMC_SDNCAS*% X44441800Y17863600D03* -%TO.P,U4,190*% -%TO.N,ARM_LED4*% X44941800Y17863600D03* -%TO.P,U4,189*% -%TO.N,ARM_LED3*% X45441800Y17863600D03* -%TO.P,U4,188*% -%TO.N,ARM_LED2*% X45941800Y17863600D03* -%TO.P,U4,187*% -%TO.N,ARM_LED1*% X46441800Y17863600D03* -%TO.P,U4,186*% -%TO.N,N/C*% X46941800Y17863600D03* -%TO.P,U4,185*% -%TO.N,VCCO_3V3*% X47441800Y17863600D03* -%TO.P,U4,184*% -%TO.N,GND*% X47941800Y17863600D03* -%TO.P,U4,183*% -%TO.N,FMC_A25*% X48441800Y17863600D03* -%TO.P,U4,182*% -%TO.N,FMC_A24*% X48941800Y17863600D03* -%TO.P,U4,181*% -%TO.N,N/C*% X49441800Y17863600D03* -%TO.P,U4,180*% X49941800Y17863600D03* -%TO.P,U4,179*% X50441800Y17863600D03* -%TO.P,U4,178*% X50941800Y17863600D03* -%TO.P,U4,177*% -%TO.N,FPGA_DONE*% X51441800Y17863600D03* -%TO.P,U4,176*% -%TO.N,N/C*% X51941800Y17863600D03* -%TO.P,U4,175*% -%TO.N,FPGA_IRQ_N_3*% X52441800Y17863600D03* -%TO.P,U4,174*% -%TO.N,FPGA_IRQ_N_2*% X52941800Y17863600D03* -%TO.P,U4,173*% -%TO.N,FMC_NE1*% X53441800Y17863600D03* -%TO.P,U4,172*% -%TO.N,FMC_NWAIT*% X53941800Y17863600D03* -%TO.P,U4,171*% -%TO.N,VCCO_3V3*% X54441800Y17863600D03* -%TO.P,U4,170*% -%TO.N,GND*% X54941800Y17863600D03* -%TO.P,U4,169*% -%TO.N,FMC_NWE*% X55441800Y17863600D03* -%TO.P,U4,168*% -%TO.N,FMC_NOE*% X55941800Y17863600D03* -%TO.P,U4,167*% -%TO.N,FMC_CLK*% X56441800Y17863600D03* -%TO.P,U4,166*% -%TO.N,N/C*% X56941800Y17863600D03* -%TO.P,U4,165*% -%TO.N,FMC_D3*% X57441800Y17863600D03* -%TO.P,U4,164*% -%TO.N,FMC_D2*% X57941800Y17863600D03* -%TO.P,U4,163*% -%TO.N,N/C*% X58441800Y17863600D03* -%TO.P,U4,162*% X58941800Y17863600D03* -%TO.P,U4,161*% X59441800Y17863600D03* -%TO.P,U4,160*% X59941800Y17863600D03* -%TO.P,U4,159*% -%TO.N,SWDCLK*% X60441800Y17863600D03* -%TO.P,U4,158*% -%TO.N,VCCO_3V3*% X60941800Y17863600D03* -%TO.P,U4,157*% -%TO.N,FMC_D27*% X61441800Y17863600D03* D40* -%TO.P,U4,156*% -%TO.N,FMC_D26*% X63441800Y19863600D03* -%TO.P,U4,155*% -%TO.N,FMC_D25*% X63441800Y20363600D03* -%TO.P,U4,154*% -%TO.N,FMC_D24*% X63441800Y20863600D03* -%TO.P,U4,153*% -%TO.N,FMC_D23*% X63441800Y21363600D03* -%TO.P,U4,152*% -%TO.N,FMC_D22*% X63441800Y21863600D03* -%TO.P,U4,151*% -%TO.N,FMC_D21*% X63441800Y22363600D03* -%TO.P,U4,150*% -%TO.N,VCCO_3V3*% X63441800Y22863600D03* -%TO.P,U4,149*% -%TO.N,GND*% X63441800Y23363600D03* -%TO.P,U4,148*% -%TO.N,VCAP2*% X63441800Y23863600D03* -%TO.P,U4,147*% -%TO.N,SWDIO*% X63441800Y24363600D03* -%TO.P,U4,146*% -%TO.N,FT_MGMT_CTS*% X63441800Y24863600D03* -%TO.P,U4,145*% -%TO.N,FT_MGMT_RTS*% X63441800Y25363600D03* -%TO.P,U4,144*% -%TO.N,FT_MGMT_TXD*% X63441800Y25863600D03* -%TO.P,U4,143*% -%TO.N,FT_MGMT_RXD*% X63441800Y26363600D03* -%TO.P,U4,142*% -%TO.N,FT_MGMT_DTR*% X63441800Y26863600D03* -%TO.P,U4,141*% -%TO.N,N/C*% X63441800Y27363600D03* -%TO.P,U4,140*% X63441800Y27863600D03* -%TO.P,U4,139*% X63441800Y28363600D03* -%TO.P,U4,138*% X63441800Y28863600D03* -%TO.P,U4,137*% -%TO.N,VCCO_3V3*% X63441800Y29363600D03* -%TO.P,U4,136*% -%TO.N,GND*% X63441800Y29863600D03* -%TO.P,U4,135*% -%TO.N,FMC_SDCLK*% X63441800Y30363600D03* -%TO.P,U4,134*% -%TO.N,N/C*% X63441800Y30863600D03* -%TO.P,U4,133*% X63441800Y31363600D03* -%TO.P,U4,132*% -%TO.N,FMC_A15*% X63441800Y31863600D03* -%TO.P,U4,131*% -%TO.N,FMC_A14*% X63441800Y32363600D03* -%TO.P,U4,130*% -%TO.N,FMC_A13*% X63441800Y32863600D03* -%TO.P,U4,129*% -%TO.N,FMC_A12*% X63441800Y33363600D03* -%TO.P,U4,128*% -%TO.N,N/C*% X63441800Y33863600D03* -%TO.P,U4,127*% X63441800Y34363600D03* -%TO.P,U4,126*% X63441800Y34863600D03* -%TO.P,U4,125*% -%TO.N,GND*% X63441800Y35363600D03* -%TO.P,U4,124*% -%TO.N,VCCO_3V3*% X63441800Y35863600D03* -%TO.P,U4,123*% -%TO.N,FPGA_IRQ_N_1*% X63441800Y36363600D03* -%TO.P,U4,122*% -%TO.N,FPGA_IRQ_N_0*% X63441800Y36863600D03* -%TO.P,U4,121*% -%TO.N,N/C*% X63441800Y37363600D03* -%TO.P,U4,120*% -%TO.N,FPGA_PROGRAM_B*% X63441800Y37863600D03* -%TO.P,U4,119*% -%TO.N,FPGA_INIT_B*% X63441800Y38363600D03* -%TO.P,U4,118*% -%TO.N,N/C*% X63441800Y38863600D03* -%TO.P,U4,117*% -%TO.N,FMC_D1*% X63441800Y39363600D03* -%TO.P,U4,116*% -%TO.N,FMC_D0*% X63441800Y39863600D03* -%TO.P,U4,115*% -%TO.N,VCCO_3V3*% X63441800Y40363600D03* -%TO.P,U4,114*% -%TO.N,GND*% X63441800Y40863600D03* -%TO.P,U4,113*% -%TO.N,FMC_A18*% X63441800Y41363600D03* -%TO.P,U4,112*% -%TO.N,FMC_A17*% X63441800Y41863600D03* -%TO.P,U4,111*% -%TO.N,FMC_A16*% X63441800Y42363600D03* -%TO.P,U4,110*% -%TO.N,FMC_D15*% X63441800Y42863600D03* -%TO.P,U4,109*% -%TO.N,FMC_D14*% X63441800Y43363600D03* -%TO.P,U4,108*% -%TO.N,FMC_D13*% X63441800Y43863600D03* -%TO.P,U4,107*% -%TO.N,ARM_FPGA_CFG_MOSI*% X63441800Y44363600D03* -%TO.P,U4,106*% -%TO.N,ARM_FPGA_CFG_MISO*% X63441800Y44863600D03* -%TO.P,U4,105*% -%TO.N,ARM_FPGA_CFG_SCLK*% X63441800Y45363600D03* D39* -%TO.P,U4,104*% -%TO.N,ARM_FPGA_CFG_CS_N*% X61441800Y47363600D03* -%TO.P,U4,103*% -%TO.N,VCCO_3V3*% X60941800Y47363600D03* -%TO.P,U4,102*% -%TO.N,FMC_D20*% X60441800Y47363600D03* -%TO.P,U4,101*% -%TO.N,FMC_D19*% X59941800Y47363600D03* -%TO.P,U4,100*% -%TO.N,FMC_D18*% X59441800Y47363600D03* -%TO.P,U4,99*% -%TO.N,FMC_D17*% X58941800Y47363600D03* -%TO.P,U4,98*% -%TO.N,FMC_D16*% X58441800Y47363600D03* -%TO.P,U4,97*% -%TO.N,AVR_GPIO_ARM_0*% X57941800Y47363600D03* -%TO.P,U4,96*% -%TO.N,AVR_GPIO_ARM_1*% X57441800Y47363600D03* -%TO.P,U4,95*% -%TO.N,N/C*% X56941800Y47363600D03* -%TO.P,U4,94*% -%TO.N,VCCO_3V3*% X56441800Y47363600D03* -%TO.P,U4,93*% -%TO.N,GND*% X55941800Y47363600D03* -%TO.P,U4,92*% -%TO.N,VCAP1*% X55441800Y47363600D03* -%TO.P,U4,91*% -%TO.N,AVR_GPIO_ARM_2*% X54941800Y47363600D03* -%TO.P,U4,90*% -%TO.N,AVR_GPIO_ARM_3*% X54441800Y47363600D03* -%TO.P,U4,89*% -%TO.N,FMC_D12*% X53941800Y47363600D03* -%TO.P,U4,88*% -%TO.N,FMC_D11*% X53441800Y47363600D03* -%TO.P,U4,87*% -%TO.N,FMC_D10*% X52941800Y47363600D03* -%TO.P,U4,86*% -%TO.N,FMC_D9*% X52441800Y47363600D03* -%TO.P,U4,85*% -%TO.N,FMC_D8*% X51941800Y47363600D03* -%TO.P,U4,84*% -%TO.N,FMC_D7*% X51441800Y47363600D03* -%TO.P,U4,83*% -%TO.N,VCCO_3V3*% X50941800Y47363600D03* -%TO.P,U4,82*% -%TO.N,GND*% X50441800Y47363600D03* -%TO.P,U4,81*% -%TO.N,FMC_D6*% X49941800Y47363600D03* -%TO.P,U4,80*% -%TO.N,FMC_D5*% X49441800Y47363600D03* -%TO.P,U4,79*% -%TO.N,FMC_D4*% X48941800Y47363600D03* -%TO.P,U4,78*% -%TO.N,FMC_A11*% X48441800Y47363600D03* -%TO.P,U4,77*% -%TO.N,FMC_A10*% X47941800Y47363600D03* -%TO.P,U4,76*% -%TO.N,FMC_A9*% X47441800Y47363600D03* -%TO.P,U4,75*% -%TO.N,FMC_A8*% X46941800Y47363600D03* -%TO.P,U4,74*% -%TO.N,FMC_A7*% X46441800Y47363600D03* -%TO.P,U4,73*% -%TO.N,VCCO_3V3*% X45941800Y47363600D03* -%TO.P,U4,72*% -%TO.N,GND*% X45441800Y47363600D03* -%TO.P,U4,71*% -%TO.N,FMC_A6*% X44941800Y47363600D03* -%TO.P,U4,70*% -%TO.N,FMC_SDNRAS*% X44441800Y47363600D03* -%TO.P,U4,69*% -%TO.N,N/C*% X43941800Y47363600D03* -%TO.P,U4,68*% X43441800Y47363600D03* -%TO.P,U4,67*% X42941800Y47363600D03* -%TO.P,U4,66*% X42441800Y47363600D03* -%TO.P,U4,65*% X41941800Y47363600D03* -%TO.P,U4,64*% X41441800Y47363600D03* -%TO.P,U4,63*% X40941800Y47363600D03* -%TO.P,U4,62*% X40441800Y47363600D03* -%TO.P,U4,61*% -%TO.N,KSM_PROM_CS_N*% X39941800Y47363600D03* -%TO.P,U4,60*% -%TO.N,GND*% X39441800Y47363600D03* -%TO.P,U4,59*% -%TO.N,VCCO_3V3*% X38941800Y47363600D03* -%TO.P,U4,58*% -%TO.N,N/C*% X38441800Y47363600D03* -%TO.P,U4,57*% X37941800Y47363600D03* -%TO.P,U4,56*% -%TO.N,KSM_PROM_MOSI*% X37441800Y47363600D03* -%TO.P,U4,55*% -%TO.N,KSM_PROM_MISO*% X36941800Y47363600D03* -%TO.P,U4,54*% -%TO.N,KSM_PROM_SCLK*% X36441800Y47363600D03* -%TO.P,U4,53*% -%TO.N,FT_DTR*% X35941800Y47363600D03* D40* -%TO.P,U4,52*% -%TO.N,VCCO_3V3*% X33941800Y45363600D03* -%TO.P,U4,51*% -%TO.N,GND*% X33941800Y44863600D03* -%TO.P,U4,50*% -%TO.N,FT_TXD*% X33941800Y44363600D03* -%TO.P,U4,49*% -%TO.N,RTC_SDA*% X33941800Y43863600D03* -%TO.P,U4,48*% -%TO.N,RTC_SCL*% X33941800Y43363600D03* -%TO.P,U4,47*% -%TO.N,RTC_MFP*% X33941800Y42863600D03* -%TO.P,U4,46*% -%TO.N,N/C*% X33941800Y42363600D03* -%TO.P,U4,45*% -%TO.N,FT_RXD*% X33941800Y41863600D03* -%TO.P,U4,44*% -%TO.N,FT_CTS*% X33941800Y41363600D03* -%TO.P,U4,43*% -%TO.N,FT_RTS*% X33941800Y40863600D03* -%TO.P,U4,42*% -%TO.N,VCCO_3V3*% X33941800Y40363600D03* -%TO.P,U4,41*% X33941800Y39863600D03* -%TO.P,U4,40*% -%TO.N,GND*% X33941800Y39363600D03* -%TO.P,U4,39*% -%TO.N,VCCO_3V3*% X33941800Y38863600D03* -%TO.P,U4,38*% -%TO.N,FMC_SDCKE0*% X33941800Y38363600D03* -%TO.P,U4,37*% -%TO.N,FMC_SDNE0*% X33941800Y37863600D03* -%TO.P,U4,36*% -%TO.N,N/C*% X33941800Y37363600D03* -%TO.P,U4,35*% -%TO.N,FMC_SDNWE*% X33941800Y36863600D03* -%TO.P,U4,34*% -%TO.N,NRST*% X33941800Y36363600D03* -%TO.P,U4,33*% -%TO.N,OSC_OUT*% X33941800Y35863600D03* -%TO.P,U4,32*% -%TO.N,OSC_IN*% X33941800Y35363600D03* -%TO.P,U4,31*% -%TO.N,N/C*% X33941800Y34863600D03* -%TO.P,U4,30*% X33941800Y34363600D03* -%TO.P,U4,29*% X33941800Y33863600D03* -%TO.P,U4,28*% X33941800Y33363600D03* -%TO.P,U4,27*% -%TO.N,FPGA_CFG_CTRL_ARM_ENA*% X33941800Y32863600D03* -%TO.P,U4,26*% -%TO.N,VCCO_3V3*% X33941800Y32363600D03* -%TO.P,U4,25*% -%TO.N,GND*% X33941800Y31863600D03* -%TO.P,U4,24*% -%TO.N,FMC_A5*% X33941800Y31363600D03* -%TO.P,U4,23*% -%TO.N,FMC_A4*% X33941800Y30863600D03* -%TO.P,U4,22*% -%TO.N,FMC_A3*% X33941800Y30363600D03* -%TO.P,U4,21*% -%TO.N,FPGA_CFG_CTRL_FPGA_DIS*% X33941800Y29863600D03* -%TO.P,U4,20*% -%TO.N,N/C*% X33941800Y29363600D03* -%TO.P,U4,19*% X33941800Y28863600D03* -%TO.P,U4,18*% -%TO.N,FMC_A2*% X33941800Y28363600D03* -%TO.P,U4,17*% -%TO.N,FMC_A1*% X33941800Y27863600D03* -%TO.P,U4,16*% -%TO.N,FMC_A0*% X33941800Y27363600D03* -%TO.P,U4,15*% -%TO.N,VCCO_3V3*% X33941800Y26863600D03* -%TO.P,U4,14*% -%TO.N,GND*% X33941800Y26363600D03* -%TO.P,U4,13*% -%TO.N,N/C*% X33941800Y25863600D03* -%TO.P,U4,12*% -%TO.N,FMC_D31*% X33941800Y25363600D03* -%TO.P,U4,11*% -%TO.N,FMC_D30*% X33941800Y24863600D03* -%TO.P,U4,10*% -%TO.N,N/C*% X33941800Y24363600D03* -%TO.P,U4,9*% X33941800Y23863600D03* -%TO.P,U4,8*% X33941800Y23363600D03* -%TO.P,U4,7*% X33941800Y22863600D03* -%TO.P,U4,6*% -%TO.N,NetR32_2*% X33941800Y22363600D03* -%TO.P,U4,5*% -%TO.N,FMC_A22*% X33941800Y21863600D03* -%TO.P,U4,4*% -%TO.N,FMC_A21*% X33941800Y21363600D03* -%TO.P,U4,3*% -%TO.N,FMC_A20*% X33941800Y20863600D03* -%TO.P,U4,2*% -%TO.N,FMC_A19*% X33941800Y20363600D03* -%TO.P,U4,1*% -%TO.N,FMC_A23*% X33941800Y19863600D03* -%TD*% -%TO.P,U6,1*% -%TO.N,VCCO_3V3*% X74920400Y39326400D03* -%TO.P,U6,2*% -%TO.N,FMC_D0*% X74920400Y39826400D03* -%TO.P,U6,3*% -%TO.N,VCCO_3V3*% X74920400Y40326400D03* -%TO.P,U6,4*% -%TO.N,FMC_D1*% X74920400Y40826400D03* -%TO.P,U6,5*% -%TO.N,FMC_D2*% X74920400Y41326400D03* -%TO.P,U6,6*% -%TO.N,GND*% X74920400Y41826400D03* -%TO.P,U6,7*% -%TO.N,FMC_D3*% X74920400Y42326400D03* -%TO.P,U6,8*% -%TO.N,FMC_D4*% X74920400Y42826400D03* -%TO.P,U6,9*% -%TO.N,N/C*% X74920400Y43326400D03* -%TO.P,U6,10*% -%TO.N,FMC_D5*% X74920400Y43826400D03* -%TO.P,U6,11*% -%TO.N,FMC_D6*% X74920400Y44326400D03* -%TO.P,U6,12*% -%TO.N,GND*% X74920400Y44826400D03* -%TO.P,U6,13*% -%TO.N,FMC_D7*% X74920400Y45326400D03* -%TO.P,U6,14*% -%TO.N,N/C*% X74920400Y45826400D03* -%TO.P,U6,15*% -%TO.N,VCCO_3V3*% X74920400Y46326400D03* -%TO.P,U6,16*% -%TO.N,FMC_NBL0*% X74920400Y46826400D03* -%TO.P,U6,17*% -%TO.N,FMC_SDNWE*% X74920400Y47326400D03* -%TO.P,U6,18*% -%TO.N,FMC_SDNCAS*% X74920400Y47826400D03* -%TO.P,U6,19*% -%TO.N,FMC_SDNRAS*% X74920400Y48326400D03* -%TO.P,U6,20*% -%TO.N,FMC_SDNE1*% X74920400Y48826400D03* -%TO.P,U6,21*% -%TO.N,FMC_A11*% X74920400Y49326400D03* -%TO.P,U6,22*% -%TO.N,FMC_A14*% X74920400Y49826400D03* -%TO.P,U6,23*% -%TO.N,FMC_A15*% X74920400Y50326400D03* -%TO.P,U6,24*% -%TO.N,FMC_A10*% X74920400Y50826400D03* -%TO.P,U6,25*% -%TO.N,FMC_A0*% X74920400Y51326400D03* -%TO.P,U6,26*% -%TO.N,FMC_A1*% X74920400Y51826400D03* -%TO.P,U6,27*% -%TO.N,FMC_A2*% X74920400Y52326400D03* -%TO.P,U6,28*% -%TO.N,FMC_NBL2*% X74920400Y52826400D03* -%TO.P,U6,29*% -%TO.N,VCCO_3V3*% X74920400Y53326400D03* -%TO.P,U6,30*% -%TO.N,N/C*% X74920400Y53826400D03* -%TO.P,U6,31*% -%TO.N,FMC_D16*% X74920400Y54326400D03* -%TO.P,U6,32*% -%TO.N,GND*% X74920400Y54826400D03* -%TO.P,U6,33*% -%TO.N,FMC_D17*% X74920400Y55326400D03* -%TO.P,U6,34*% -%TO.N,FMC_D18*% X74920400Y55826400D03* -%TO.P,U6,35*% -%TO.N,VCCO_3V3*% X74920400Y56326400D03* -%TO.P,U6,36*% -%TO.N,FMC_D19*% X74920400Y56826400D03* -%TO.P,U6,37*% -%TO.N,FMC_D20*% X74920400Y57326400D03* -%TO.P,U6,38*% -%TO.N,GND*% X74920400Y57826400D03* -%TO.P,U6,39*% -%TO.N,FMC_D21*% X74920400Y58326400D03* -%TO.P,U6,40*% -%TO.N,FMC_D22*% X74920400Y58826400D03* -%TO.P,U6,41*% -%TO.N,VCCO_3V3*% X74920400Y59326400D03* -%TO.P,U6,42*% -%TO.N,FMC_D23*% X74920400Y59826400D03* -%TO.P,U6,43*% -%TO.N,VCCO_3V3*% X74920400Y60326400D03* -%TO.P,U6,86*% -%TO.N,GND*% X86420400Y39326400D03* -%TO.P,U6,85*% -%TO.N,FMC_D15*% X86420400Y39826400D03* -%TO.P,U6,84*% -%TO.N,GND*% X86420400Y40326400D03* -%TO.P,U6,83*% -%TO.N,FMC_D14*% X86420400Y40826400D03* -%TO.P,U6,82*% -%TO.N,FMC_D13*% X86420400Y41326400D03* -%TO.P,U6,81*% -%TO.N,VCCO_3V3*% X86420400Y41826400D03* -%TO.P,U6,80*% -%TO.N,FMC_D12*% X86420400Y42326400D03* -%TO.P,U6,79*% -%TO.N,FMC_D11*% X86420400Y42826400D03* -%TO.P,U6,78*% -%TO.N,GND*% X86420400Y43326400D03* -%TO.P,U6,77*% -%TO.N,FMC_D10*% X86420400Y43826400D03* -%TO.P,U6,76*% -%TO.N,FMC_D9*% X86420400Y44326400D03* -%TO.P,U6,75*% -%TO.N,VCCO_3V3*% X86420400Y44826400D03* -%TO.P,U6,74*% -%TO.N,FMC_D8*% X86420400Y45326400D03* -%TO.P,U6,73*% -%TO.N,N/C*% X86420400Y45826400D03* -%TO.P,U6,72*% -%TO.N,GND*% X86420400Y46326400D03* -%TO.P,U6,71*% -%TO.N,FMC_NBL1*% X86420400Y46826400D03* -%TO.P,U6,70*% -%TO.N,N/C*% X86420400Y47326400D03* -%TO.P,U6,69*% -%TO.N,FMC_A12*% X86420400Y47826400D03* -%TO.P,U6,68*% -%TO.N,FMC_SDCLK*% X86420400Y48326400D03* -%TO.P,U6,67*% -%TO.N,FMC_SDCKE1*% X86420400Y48826400D03* -%TO.P,U6,66*% -%TO.N,FMC_A9*% X86420400Y49326400D03* -%TO.P,U6,65*% -%TO.N,FMC_A8*% X86420400Y49826400D03* -%TO.P,U6,64*% -%TO.N,FMC_A7*% X86420400Y50326400D03* -%TO.P,U6,63*% -%TO.N,FMC_A6*% X86420400Y50826400D03* -%TO.P,U6,62*% -%TO.N,FMC_A5*% X86420400Y51326400D03* -%TO.P,U6,61*% -%TO.N,FMC_A4*% X86420400Y51826400D03* -%TO.P,U6,60*% -%TO.N,FMC_A3*% X86420400Y52326400D03* -%TO.P,U6,59*% -%TO.N,FMC_NBL3*% X86420400Y52826400D03* -%TO.P,U6,58*% -%TO.N,GND*% X86420400Y53326400D03* -%TO.P,U6,57*% -%TO.N,N/C*% X86420400Y53826400D03* -%TO.P,U6,56*% -%TO.N,FMC_D31*% X86420400Y54326400D03* -%TO.P,U6,55*% -%TO.N,VCCO_3V3*% X86420400Y54826400D03* -%TO.P,U6,54*% -%TO.N,FMC_D30*% X86420400Y55326400D03* -%TO.P,U6,53*% -%TO.N,FMC_D29*% X86420400Y55826400D03* -%TO.P,U6,52*% -%TO.N,GND*% X86420400Y56326400D03* -%TO.P,U6,51*% -%TO.N,FMC_D28*% X86420400Y56826400D03* -%TO.P,U6,50*% -%TO.N,FMC_D27*% X86420400Y57326400D03* -%TO.P,U6,49*% -%TO.N,VCCO_3V3*% X86420400Y57826400D03* -%TO.P,U6,48*% -%TO.N,FMC_D26*% X86420400Y58326400D03* -%TO.P,U6,47*% -%TO.N,FMC_D25*% X86420400Y58826400D03* -%TO.P,U6,46*% -%TO.N,GND*% X86420400Y59326400D03* -%TO.P,U6,45*% -%TO.N,FMC_D24*% X86420400Y59826400D03* -%TO.P,U6,44*% -%TO.N,GND*% X86420400Y60326400D03* -%TD*% D41* -%TO.P,U12,1*% -%TO.N,MKM_CS_N*% X78536800Y33435800D03* -%TO.P,U12,2*% -%TO.N,MKM_MISO*% X79806800Y33435800D03* -%TO.P,U12,3*% -%TO.N,N/C*% X81076800Y33435800D03* -%TO.P,U12,4*% -%TO.N,GND*% X82346800Y33435800D03* -%TO.P,U12,5*% -%TO.N,MKM_MOSI*% X82346800Y28025600D03* -%TO.P,U12,6*% -%TO.N,MKM_SCK*% X81076800Y28025600D03* -%TO.P,U12,7*% -%TO.N,NetR33_2*% X79806800Y28025600D03* -%TO.P,U12,8*% -%TO.N,3V3_BATT*% X78536800Y28025600D03* -%TD*% D42* -%TO.P,U13,AB22*% -%TO.N,FMC_A20*% X45953400Y58384800D03* -%TO.P,U13,AB21*% -%TO.N,FMC_A19*% X46953400Y58384800D03* -%TO.P,U13,AB20*% -%TO.N,FMC_A21*% X47953400Y58384800D03* -%TO.P,U13,AB19*% -%TO.N,GND*% X48953400Y58384800D03* -%TO.P,U13,AB18*% -%TO.N,FMC_A24*% X49953400Y58384800D03* -%TO.P,U13,AB17*% -%TO.N,FMC_A4*% X50953400Y58384800D03* -%TO.P,U13,AB16*% -%TO.N,FMC_A1*% X51953400Y58384800D03* -%TO.P,U13,AB15*% -%TO.N,FMC_A8*% X52953400Y58384800D03* -%TO.P,U13,AB14*% -%TO.N,VCCO_3V3*% X53953400Y58384800D03* -%TO.P,U13,AB13*% -%TO.N,FMC_A6*% X54953400Y58384800D03* -%TO.P,U13,AB12*% -%TO.N,FMC_A14*% X55953400Y58384800D03* -%TO.P,U13,AB11*% -%TO.N,FMC_D4*% X56953400Y58384800D03* -%TO.P,U13,AB10*% -%TO.N,FMC_A12*% X57953400Y58384800D03* -%TO.P,U13,AB9*% -%TO.N,GND*% X58953400Y58384800D03* -%TO.P,U13,AB8*% -%TO.N,FMC_A15*% X59953400Y58384800D03* -%TO.P,U13,AB7*% -%TO.N,FMC_D0*% X60953400Y58384800D03* -%TO.P,U13,AB6*% -%TO.N,FMC_D1*% X61953400Y58384800D03* -%TO.P,U13,AB5*% -%TO.N,FMC_D20*% X62953400Y58384800D03* -%TO.P,U13,AB4*% -%TO.N,VCCO_3V3*% X63953400Y58384800D03* -%TO.P,U13,AB3*% -%TO.N,FMC_D16*% X64953400Y58384800D03* -%TO.P,U13,AB2*% -%TO.N,FMC_D15*% X65953400Y58384800D03* -%TO.P,U13,AB1*% -%TO.N,FMC_D14*% X66953400Y58384800D03* -%TO.P,U13,AA22*% -%TO.N,GND*% X45953400Y59384800D03* -%TO.P,U13,AA21*% -%TO.N,FMC_D9*% X46953400Y59384800D03* -%TO.P,U13,AA20*% -%TO.N,FPGA_GPIO_LED_3*% X47953400Y59384800D03* -%TO.P,U13,AA19*% -%TO.N,FMC_A25*% X48953400Y59384800D03* -%TO.P,U13,AA18*% -%TO.N,N/C*% X49953400Y59384800D03* -%TO.P,U13,AA17*% -%TO.N,VCCO_3V3*% X50953400Y59384800D03* -%TO.P,U13,AA16*% -%TO.N,FMC_A2*% X51953400Y59384800D03* -%TO.P,U13,AA15*% -%TO.N,FMC_A7*% X52953400Y59384800D03* -%TO.P,U13,AA14*% -%TO.N,FMC_A10*% X53953400Y59384800D03* -%TO.P,U13,AA13*% -%TO.N,FMC_A5*% X54953400Y59384800D03* -%TO.P,U13,AA12*% -%TO.N,GND*% X55953400Y59384800D03* -%TO.P,U13,AA11*% -%TO.N,FMC_D5*% X56953400Y59384800D03* -%TO.P,U13,AA10*% -%TO.N,N/C*% X57953400Y59384800D03* -%TO.P,U13,AA9*% -%TO.N,FMC_A16*% X58953400Y59384800D03* -%TO.P,U13,AA8*% -%TO.N,FMC_A17*% X59953400Y59384800D03* -%TO.P,U13,AA7*% -%TO.N,VCCO_3V3*% X60953400Y59384800D03* -%TO.P,U13,AA6*% -%TO.N,FMC_NWE*% X61953400Y59384800D03* -%TO.P,U13,AA5*% -%TO.N,FMC_D19*% X62953400Y59384800D03* -%TO.P,U13,AA4*% -%TO.N,FMC_D22*% X63953400Y59384800D03* -%TO.P,U13,AA3*% -%TO.N,FMC_D18*% X64953400Y59384800D03* -%TO.P,U13,AA2*% -%TO.N,GND*% X65953400Y59384800D03* -%TO.P,U13,AA1*% -%TO.N,FMC_D13*% X66953400Y59384800D03* -%TO.P,U13,Y22*% -%TO.N,FMC_A23*% X45953400Y60384800D03* -%TO.P,U13,Y21*% -%TO.N,FMC_A22*% X46953400Y60384800D03* -%TO.P,U13,Y20*% -%TO.N,VCCO_3V3*% X47953400Y60384800D03* -%TO.P,U13,Y19*% -%TO.N,N/C*% X48953400Y60384800D03* -%TO.P,U13,Y18*% -%TO.N,FMC_D8*% X49953400Y60384800D03* -%TO.P,U13,Y17*% -%TO.N,FMC_A0*% X50953400Y60384800D03* -%TO.P,U13,Y16*% -%TO.N,FMC_A3*% X51953400Y60384800D03* -%TO.P,U13,Y15*% -%TO.N,GND*% X52953400Y60384800D03* -%TO.P,U13,Y14*% -%TO.N,FMC_A11*% X53953400Y60384800D03* -%TO.P,U13,Y13*% -%TO.N,FMC_A9*% X54953400Y60384800D03* -%TO.P,U13,Y12*% -%TO.N,FMC_D7*% X55953400Y60384800D03* -%TO.P,U13,Y11*% -%TO.N,FMC_D6*% X56953400Y60384800D03* -%TO.P,U13,Y10*% -%TO.N,VCCO_3V3*% X57953400Y60384800D03* -%TO.P,U13,Y9*% -%TO.N,N/C*% X58953400Y60384800D03* -%TO.P,U13,Y8*% X59953400Y60384800D03* -%TO.P,U13,Y7*% -%TO.N,FMC_A18*% X60953400Y60384800D03* -%TO.P,U13,Y6*% -%TO.N,FMC_NWAIT*% X61953400Y60384800D03* -%TO.P,U13,Y5*% -%TO.N,GND*% X62953400Y60384800D03* -%TO.P,U13,Y4*% -%TO.N,FMC_D21*% X63953400Y60384800D03* -%TO.P,U13,Y3*% -%TO.N,FMC_D17*% X64953400Y60384800D03* -%TO.P,U13,Y2*% -%TO.N,N/C*% X65953400Y60384800D03* -%TO.P,U13,Y1*% -%TO.N,MKM_FPGA_MISO*% X66953400Y60384800D03* -%TO.P,U13,W22*% -%TO.N,FPGA_GPIO_LED_2*% X45953400Y61384800D03* -%TO.P,U13,W21*% -%TO.N,N/C*% X46953400Y61384800D03* -%TO.P,U13,W20*% -%TO.N,FMC_D10*% X47953400Y61384800D03* -%TO.P,U13,W19*% -%TO.N,DIGITIZED_NOISE*% X48953400Y61384800D03* -%TO.P,U13,W18*% -%TO.N,GND*% X49953400Y61384800D03* -%TO.P,U13,W17*% -%TO.N,FMC_NL*% X50953400Y61384800D03* -%TO.P,U13,W16*% -%TO.N,FMC_NOE*% X51953400Y61384800D03* -%TO.P,U13,W15*% -%TO.N,N/C*% X52953400Y61384800D03* -%TO.P,U13,W14*% -%TO.N,FMC_D27*% X53953400Y61384800D03* -%TO.P,U13,W13*% -%TO.N,VCCO_3V3*% X54953400Y61384800D03* -%TO.P,U13,W12*% -%TO.N,FMC_D26*% X55953400Y61384800D03* -%TO.P,U13,W11*% -%TO.N,FMC_CLK*% X56953400Y61384800D03* -%TO.P,U13,W10*% -%TO.N,FMC_D24*% X57953400Y61384800D03* -%TO.P,U13,W9*% -%TO.N,N/C*% X58953400Y61384800D03* -%TO.P,U13,W8*% -%TO.N,GND*% X59953400Y61384800D03* -%TO.P,U13,W7*% -%TO.N,N/C*% X60953400Y61384800D03* -%TO.P,U13,W6*% X61953400Y61384800D03* -%TO.P,U13,W5*% X62953400Y61384800D03* -%TO.P,U13,W4*% X63953400Y61384800D03* -%TO.P,U13,W3*% -%TO.N,VCCO_3V3*% X64953400Y61384800D03* -%TO.P,U13,W2*% -%TO.N,MKM_FPGA_CS_N*% X65953400Y61384800D03* -%TO.P,U13,W1*% -%TO.N,MKM_FPGA_MOSI*% X66953400Y61384800D03* -%TO.P,U13,V22*% -%TO.N,N/C*% X45953400Y62384800D03* -%TO.P,U13,V21*% -%TO.N,GND*% X46953400Y62384800D03* -%TO.P,U13,V20*% -%TO.N,FMC_D28*% X47953400Y62384800D03* -%TO.P,U13,V19*% -%TO.N,N/C*% X48953400Y62384800D03* -%TO.P,U13,V18*% -%TO.N,FMC_D29*% X49953400Y62384800D03* -%TO.P,U13,V17*% -%TO.N,N/C*% X50953400Y62384800D03* -%TO.P,U13,V16*% -%TO.N,VCCO_3V3*% X51953400Y62384800D03* -%TO.P,U13,V15*% -%TO.N,N/C*% X52953400Y62384800D03* -%TO.P,U13,V14*% X53953400Y62384800D03* -%TO.P,U13,V13*% X54953400Y62384800D03* -%TO.P,U13,V12*% -%TO.N,FPGA_JTAG_TCK*% X55953400Y62384800D03* -%TO.P,U13,V11*% -%TO.N,GND*% X56953400Y62384800D03* -%TO.P,U13,V10*% -%TO.N,N/C*% X57953400Y62384800D03* -%TO.P,U13,V9*% X58953400Y62384800D03* -%TO.P,U13,V8*% X59953400Y62384800D03* -%TO.P,U13,V7*% X60953400Y62384800D03* -%TO.P,U13,V6*% -%TO.N,VCCO_3V3*% X61953400Y62384800D03* -%TO.P,U13,V5*% -%TO.N,FMC_NE1*% X62953400Y62384800D03* -%TO.P,U13,V4*% -%TO.N,FMC_D23*% X63953400Y62384800D03* -%TO.P,U13,V3*% -%TO.N,MKM_FPGA_SCK*% X64953400Y62384800D03* -%TO.P,U13,V2*% -%TO.N,FMC_A13*% X65953400Y62384800D03* -%TO.P,U13,V1*% -%TO.N,GND*% X66953400Y62384800D03* -%TO.P,U13,U22*% -%TO.N,NetR65_1*% X45953400Y63384800D03* -%TO.P,U13,U21*% -%TO.N,N/C*% X46953400Y63384800D03* -%TO.P,U13,U20*% -%TO.N,FMC_D12*% X47953400Y63384800D03* -%TO.P,U13,U19*% -%TO.N,VCCO_3V3*% X48953400Y63384800D03* -%TO.P,U13,U18*% -%TO.N,N/C*% X49953400Y63384800D03* -%TO.P,U13,U17*% X50953400Y63384800D03* -%TO.P,U13,U16*% X51953400Y63384800D03* -%TO.P,U13,U15*% X52953400Y63384800D03* -%TO.P,U13,U14*% -%TO.N,GND*% X53953400Y63384800D03* -%TO.P,U13,U13*% -%TO.N,FPGA_JTAG_TDO*% X54953400Y63384800D03* -%TO.P,U13,U12*% -%TO.N,FPGA_INIT_B_INT1*% X55953400Y63384800D03* -%TO.P,U13,U11*% -%TO.N,FPGA_M0*% X56953400Y63384800D03* -%TO.P,U13,U10*% -%TO.N,FPGA_M1*% X57953400Y63384800D03* -%TO.P,U13,U9*% -%TO.N,FPGA_M2*% X58953400Y63384800D03* -%TO.P,U13,U8*% -%TO.N,VCCO_3V3*% X59953400Y63384800D03* -%TO.P,U13,U7*% -%TO.N,N/C*% X60953400Y63384800D03* -%TO.P,U13,U6*% X61953400Y63384800D03* -%TO.P,U13,U5*% X62953400Y63384800D03* -%TO.P,U13,U4*% -%TO.N,GND*% X63953400Y63384800D03* -%TO.P,U13,U3*% -%TO.N,FPGA_GPIO_LED_0*% X64953400Y63384800D03* -%TO.P,U13,U2*% -%TO.N,FMC_D3*% X65953400Y63384800D03* -%TO.P,U13,U1*% -%TO.N,FMC_D2*% X66953400Y63384800D03* -%TO.P,U13,T22*% -%TO.N,VCCO_3V3*% X45953400Y64384800D03* -%TO.P,U13,T21*% -%TO.N,N/C*% X46953400Y64384800D03* -%TO.P,U13,T20*% X47953400Y64384800D03* -%TO.P,U13,T19*% -%TO.N,FPGA_CFG_CS_N1*% X48953400Y64384800D03* -%TO.P,U13,T18*% -%TO.N,N/C*% X49953400Y64384800D03* -%TO.P,U13,T17*% -%TO.N,GND*% X50953400Y64384800D03* -%TO.P,U13,T16*% -%TO.N,N/C*% X51953400Y64384800D03* -%TO.P,U13,T15*% X52953400Y64384800D03* -%TO.P,U13,T14*% X53953400Y64384800D03* -%TO.P,U13,T13*% -%TO.N,FPGA_JTAG_TMS*% X54953400Y64384800D03* -%TO.P,U13,T12*% -%TO.N,VCCO_3V3*% X55953400Y64384800D03* -%TO.P,U13,T11*% -%TO.N,GND*% X56953400Y64384800D03* -%TO.P,U13,T10*% -%TO.N,FPGA_VCCINT_1V0*% X57953400Y64384800D03* -%TO.P,U13,T9*% -%TO.N,GND*% X58953400Y64384800D03* -%TO.P,U13,T8*% -%TO.N,FPGA_VCCINT_1V0*% X59953400Y64384800D03* -%TO.P,U13,T7*% -%TO.N,GND*% X60953400Y64384800D03* -%TO.P,U13,T6*% -%TO.N,N/C*% X61953400Y64384800D03* -%TO.P,U13,T5*% X62953400Y64384800D03* -%TO.P,U13,T4*% X63953400Y64384800D03* -%TO.P,U13,T3*% X64953400Y64384800D03* -%TO.P,U13,T2*% -%TO.N,VCCO_3V3*% X65953400Y64384800D03* -%TO.P,U13,T1*% -%TO.N,FPGA_GPIO_LED_1*% X66953400Y64384800D03* -%TO.P,U13,R22*% -%TO.N,FPGA_CFG_MISO1*% X45953400Y65384800D03* -%TO.P,U13,R21*% -%TO.N,FMC_D30*% X46953400Y65384800D03* -%TO.P,U13,R20*% -%TO.N,GND*% X47953400Y65384800D03* -%TO.P,U13,R19*% -%TO.N,N/C*% X48953400Y65384800D03* -%TO.P,U13,R18*% X49953400Y65384800D03* -%TO.P,U13,R17*% X50953400Y65384800D03* -%TO.P,U13,R16*% X51953400Y65384800D03* -%TO.P,U13,R15*% -%TO.N,VCCO_3V3*% X52953400Y65384800D03* -%TO.P,U13,R14*% -%TO.N,N/C*% X53953400Y65384800D03* -%TO.P,U13,R13*% -%TO.N,FPGA_JTAG_TDI*% X54953400Y65384800D03* -%TO.P,U13,R12*% -%TO.N,GND*% X55953400Y65384800D03* -%TO.P,U13,R11*% -%TO.N,FPGA_VCCAUX_1V8*% X56953400Y65384800D03* -%TO.P,U13,R10*% -%TO.N,GND*% X57953400Y65384800D03* -%TO.P,U13,R9*% -%TO.N,FPGA_VCCINT_1V0*% X58953400Y65384800D03* -%TO.P,U13,R8*% -%TO.N,GND*% X59953400Y65384800D03* -%TO.P,U13,R7*% -%TO.N,FPGA_VCCINT_1V0*% X60953400Y65384800D03* -%TO.P,U13,R6*% -%TO.N,N/C*% X61953400Y65384800D03* -%TO.P,U13,R5*% -%TO.N,VCCO_3V3*% X62953400Y65384800D03* -%TO.P,U13,R4*% -%TO.N,FMC_D25*% X63953400Y65384800D03* -%TO.P,U13,R3*% -%TO.N,N/C*% X64953400Y65384800D03* -%TO.P,U13,R2*% X65953400Y65384800D03* -%TO.P,U13,R1*% X66953400Y65384800D03* -%TO.P,U13,P22*% -%TO.N,FPGA_CFG_MOSI1*% X45953400Y66384800D03* -%TO.P,U13,P21*% -%TO.N,FMC_D31*% X46953400Y66384800D03* -%TO.P,U13,P20*% -%TO.N,N/C*% X47953400Y66384800D03* -%TO.P,U13,P19*% X48953400Y66384800D03* -%TO.P,U13,P18*% -%TO.N,VCCO_3V3*% X49953400Y66384800D03* -%TO.P,U13,P17*% -%TO.N,N/C*% X50953400Y66384800D03* -%TO.P,U13,P16*% X51953400Y66384800D03* -%TO.P,U13,P15*% X52953400Y66384800D03* -%TO.P,U13,P14*% X53953400Y66384800D03* -%TO.P,U13,P13*% -%TO.N,GND*% X54953400Y66384800D03* -%TO.P,U13,P12*% -%TO.N,FPGA_VCCAUX_1V8*% X55953400Y66384800D03* -%TO.P,U13,P11*% -%TO.N,GND*% X56953400Y66384800D03* -%TO.P,U13,P10*% -%TO.N,FPGA_VCCINT_1V0*% X57953400Y66384800D03* -%TO.P,U13,P9*% -%TO.N,GND*% X58953400Y66384800D03* -%TO.P,U13,P8*% -%TO.N,FPGA_VCCINT_1V0*% X59953400Y66384800D03* -%TO.P,U13,P7*% -%TO.N,GND*% X60953400Y66384800D03* -%TO.P,U13,P6*% -%TO.N,N/C*% X61953400Y66384800D03* -%TO.P,U13,P5*% X62953400Y66384800D03* -%TO.P,U13,P4*% X63953400Y66384800D03* -%TO.P,U13,P3*% -%TO.N,GND*% X64953400Y66384800D03* -%TO.P,U13,P2*% -%TO.N,N/C*% X65953400Y66384800D03* -%TO.P,U13,P1*% X66953400Y66384800D03* -%TO.P,U13,N22*% X45953400Y67384800D03* -%TO.P,U13,N21*% -%TO.N,VCCO_3V3*% X46953400Y67384800D03* -%TO.P,U13,N20*% -%TO.N,N/C*% X47953400Y67384800D03* -%TO.P,U13,N19*% X48953400Y67384800D03* -%TO.P,U13,N18*% X49953400Y67384800D03* -%TO.P,U13,N17*% X50953400Y67384800D03* -%TO.P,U13,N16*% -%TO.N,GND*% X51953400Y67384800D03* -%TO.P,U13,N15*% -%TO.N,FMC_D11*% X52953400Y67384800D03* -%TO.P,U13,N14*% -%TO.N,N/C*% X53953400Y67384800D03* -%TO.P,U13,N13*% X54953400Y67384800D03* -%TO.P,U13,N12*% -%TO.N,FPGA_PROGRAM_B1*% X55953400Y67384800D03* -%TO.P,U13,N11*% -%TO.N,FPGA_VCCINT_1V0*% X56953400Y67384800D03* -%TO.P,U13,N10*% -%TO.N,GND*% X57953400Y67384800D03* -%TO.P,U13,N9*% X58953400Y67384800D03* -%TO.P,U13,N8*% X59953400Y67384800D03* -%TO.P,U13,N7*% -%TO.N,FPGA_VCCINT_1V0*% X60953400Y67384800D03* -%TO.P,U13,N6*% -%TO.N,GND*% X61953400Y67384800D03* -%TO.P,U13,N5*% -%TO.N,N/C*% X62953400Y67384800D03* -%TO.P,U13,N4*% X63953400Y67384800D03* -%TO.P,U13,N3*% X64953400Y67384800D03* -%TO.P,U13,N2*% X65953400Y67384800D03* -%TO.P,U13,N1*% -%TO.N,VCCO_3V3*% X66953400Y67384800D03* -%TO.P,U13,M22*% -%TO.N,N/C*% X45953400Y68384800D03* -%TO.P,U13,M21*% X46953400Y68384800D03* -%TO.P,U13,M20*% X47953400Y68384800D03* -%TO.P,U13,M19*% -%TO.N,GND*% X48953400Y68384800D03* -%TO.P,U13,M18*% -%TO.N,N/C*% X49953400Y68384800D03* -%TO.P,U13,M17*% X50953400Y68384800D03* -%TO.P,U13,M16*% X51953400Y68384800D03* -%TO.P,U13,M15*% X52953400Y68384800D03* -%TO.P,U13,M14*% -%TO.N,VCCO_3V3*% X53953400Y68384800D03* -%TO.P,U13,M13*% -%TO.N,N/C*% X54953400Y68384800D03* -%TO.P,U13,M12*% -%TO.N,FPGA_VCCAUX_1V8*% X55953400Y68384800D03* -%TO.P,U13,M11*% -%TO.N,GND*% X56953400Y68384800D03* -%TO.P,U13,M10*% X57953400Y68384800D03* -%TO.P,U13,M9*% -%TO.N,N/C*% X58953400Y68384800D03* -%TO.P,U13,M8*% -%TO.N,FPGA_VCCINT_1V0*% X59953400Y68384800D03* -%TO.P,U13,M7*% -%TO.N,GND*% X60953400Y68384800D03* -%TO.P,U13,M6*% -%TO.N,N/C*% X61953400Y68384800D03* -%TO.P,U13,M5*% X62953400Y68384800D03* -%TO.P,U13,M4*% -%TO.N,VCCO_3V3*% X63953400Y68384800D03* -%TO.P,U13,M3*% -%TO.N,N/C*% X64953400Y68384800D03* -%TO.P,U13,M2*% X65953400Y68384800D03* -%TO.P,U13,M1*% X66953400Y68384800D03* -%TO.P,U13,L22*% -%TO.N,GND*% X45953400Y69384800D03* -%TO.P,U13,L21*% -%TO.N,N/C*% X46953400Y69384800D03* -%TO.P,U13,L20*% X47953400Y69384800D03* -%TO.P,U13,L19*% X48953400Y69384800D03* -%TO.P,U13,L18*% X49953400Y69384800D03* -%TO.P,U13,L17*% -%TO.N,VCCO_3V3*% X50953400Y69384800D03* -%TO.P,U13,L16*% -%TO.N,N/C*% X51953400Y69384800D03* -%TO.P,U13,L15*% X52953400Y69384800D03* -%TO.P,U13,L14*% X53953400Y69384800D03* -%TO.P,U13,L13*% X54953400Y69384800D03* -%TO.P,U13,L12*% -%TO.N,FPGA_CFG_SCLK1*% X55953400Y69384800D03* -%TO.P,U13,L11*% -%TO.N,FPGA_VCCINT_1V0*% X56953400Y69384800D03* -%TO.P,U13,L10*% -%TO.N,N/C*% X57953400Y69384800D03* -%TO.P,U13,L9*% -%TO.N,GND*% X58953400Y69384800D03* -%TO.P,U13,L8*% X59953400Y69384800D03* -%TO.P,U13,L7*% -%TO.N,FPGA_VCCINT_1V0*% X60953400Y69384800D03* -%TO.P,U13,L6*% -%TO.N,N/C*% X61953400Y69384800D03* -%TO.P,U13,L5*% X62953400Y69384800D03* -%TO.P,U13,L4*% X63953400Y69384800D03* -%TO.P,U13,L3*% X64953400Y69384800D03* -%TO.P,U13,L2*% -%TO.N,GND*% X65953400Y69384800D03* -%TO.P,U13,L1*% -%TO.N,N/C*% X66953400Y69384800D03* -%TO.P,U13,K22*% X45953400Y70384800D03* -%TO.P,U13,K21*% X46953400Y70384800D03* -%TO.P,U13,K20*% -%TO.N,VCCO_3V3*% X47953400Y70384800D03* -%TO.P,U13,K19*% -%TO.N,N/C*% X48953400Y70384800D03* -%TO.P,U13,K18*% X49953400Y70384800D03* -%TO.P,U13,K17*% X50953400Y70384800D03* -%TO.P,U13,K16*% X51953400Y70384800D03* -%TO.P,U13,K15*% -%TO.N,GND*% X52953400Y70384800D03* -%TO.P,U13,K14*% -%TO.N,N/C*% X53953400Y70384800D03* -%TO.P,U13,K13*% X54953400Y70384800D03* -%TO.P,U13,K12*% -%TO.N,FPGA_VCCAUX_1V8*% X55953400Y70384800D03* -%TO.P,U13,K11*% -%TO.N,GND*% X56953400Y70384800D03* -%TO.P,U13,K10*% -%TO.N,FPGA_VCCAUX_1V8*% X57953400Y70384800D03* -%TO.P,U13,K9*% -%TO.N,GND*% X58953400Y70384800D03* -%TO.P,U13,K8*% -%TO.N,FPGA_VCCINT_1V0*% X59953400Y70384800D03* -%TO.P,U13,K7*% -%TO.N,GND*% X60953400Y70384800D03* -%TO.P,U13,K6*% -%TO.N,N/C*% X61953400Y70384800D03* -%TO.P,U13,K5*% -%TO.N,GND*% X62953400Y70384800D03* -%TO.P,U13,K4*% -%TO.N,N/C*% X63953400Y70384800D03* -%TO.P,U13,K3*% X64953400Y70384800D03* -%TO.P,U13,K2*% X65953400Y70384800D03* -%TO.P,U13,K1*% X66953400Y70384800D03* -%TO.P,U13,J22*% X45953400Y71384800D03* -%TO.P,U13,J21*% X46953400Y71384800D03* -%TO.P,U13,J20*% X47953400Y71384800D03* -%TO.P,U13,J19*% X48953400Y71384800D03* -%TO.P,U13,J18*% -%TO.N,GND*% X49953400Y71384800D03* -%TO.P,U13,J17*% -%TO.N,N/C*% X50953400Y71384800D03* -%TO.P,U13,J16*% X51953400Y71384800D03* -%TO.P,U13,J15*% X52953400Y71384800D03* -%TO.P,U13,J14*% X53953400Y71384800D03* -%TO.P,U13,J13*% -%TO.N,VCCO_3V3*% X54953400Y71384800D03* -%TO.P,U13,J12*% -%TO.N,GND*% X55953400Y71384800D03* -%TO.P,U13,J11*% -%TO.N,FPGA_VCCINT_1V0*% X56953400Y71384800D03* -%TO.P,U13,J10*% -%TO.N,GND*% X57953400Y71384800D03* -%TO.P,U13,J9*% -%TO.N,FPGA_VCCINT_1V0*% X58953400Y71384800D03* -%TO.P,U13,J8*% -%TO.N,GND*% X59953400Y71384800D03* -%TO.P,U13,J7*% -%TO.N,FPGA_VCCINT_1V0*% X60953400Y71384800D03* -%TO.P,U13,J6*% -%TO.N,N/C*% X61953400Y71384800D03* -%TO.P,U13,J5*% X62953400Y71384800D03* -%TO.P,U13,J4*% X63953400Y71384800D03* -%TO.P,U13,J3*% -%TO.N,VCCO_3V3*% X64953400Y71384800D03* -%TO.P,U13,J2*% -%TO.N,N/C*% X65953400Y71384800D03* -%TO.P,U13,J1*% X66953400Y71384800D03* -%TO.P,U13,H22*% X45953400Y72384800D03* -%TO.P,U13,H21*% -%TO.N,GND*% X46953400Y72384800D03* -%TO.P,U13,H20*% -%TO.N,N/C*% X47953400Y72384800D03* -%TO.P,U13,H19*% X48953400Y72384800D03* -%TO.P,U13,H18*% X49953400Y72384800D03* -%TO.P,U13,H17*% X50953400Y72384800D03* -%TO.P,U13,H16*% -%TO.N,VCCO_3V3*% X51953400Y72384800D03* -%TO.P,U13,H15*% -%TO.N,N/C*% X52953400Y72384800D03* -%TO.P,U13,H14*% X53953400Y72384800D03* -%TO.P,U13,H13*% X54953400Y72384800D03* -%TO.P,U13,H12*% -%TO.N,FPGA_VCCAUX_1V8*% X55953400Y72384800D03* -%TO.P,U13,H11*% -%TO.N,GND*% X56953400Y72384800D03* -%TO.P,U13,H10*% -%TO.N,FPGA_VCCINT_1V0*% X57953400Y72384800D03* -%TO.P,U13,H9*% -%TO.N,GND*% X58953400Y72384800D03* -%TO.P,U13,H8*% -%TO.N,FPGA_VCCINT_1V0*% X59953400Y72384800D03* -%TO.P,U13,H7*% -%TO.N,GND*% X60953400Y72384800D03* -%TO.P,U13,H6*% -%TO.N,VCCO_3V3*% X61953400Y72384800D03* -%TO.P,U13,H5*% -%TO.N,N/C*% X62953400Y72384800D03* -%TO.P,U13,H4*% X63953400Y72384800D03* -%TO.P,U13,H3*% X64953400Y72384800D03* -%TO.P,U13,H2*% X65953400Y72384800D03* -%TO.P,U13,H1*% -%TO.N,GND*% X66953400Y72384800D03* -%TO.P,U13,G22*% -%TO.N,N/C*% X45953400Y73384800D03* -%TO.P,U13,G21*% X46953400Y73384800D03* -%TO.P,U13,G20*% X47953400Y73384800D03* -%TO.P,U13,G19*% -%TO.N,VCCO_3V3*% X48953400Y73384800D03* -%TO.P,U13,G18*% -%TO.N,N/C*% X49953400Y73384800D03* -%TO.P,U13,G17*% X50953400Y73384800D03* -%TO.P,U13,G16*% X51953400Y73384800D03* -%TO.P,U13,G15*% X52953400Y73384800D03* -%TO.P,U13,G14*% -%TO.N,GND*% X53953400Y73384800D03* -%TO.P,U13,G13*% -%TO.N,N/C*% X54953400Y73384800D03* -%TO.P,U13,G12*% -%TO.N,GND*% X55953400Y73384800D03* -%TO.P,U13,G11*% -%TO.N,FPGA_DONE_INT*% X56953400Y73384800D03* -%TO.P,U13,G10*% -%TO.N,GND*% X57953400Y73384800D03* -%TO.P,U13,G9*% X58953400Y73384800D03* -%TO.P,U13,G8*% X59953400Y73384800D03* -%TO.P,U13,G7*% X60953400Y73384800D03* -%TO.P,U13,G6*% X61953400Y73384800D03* -%TO.P,U13,G5*% X62953400Y73384800D03* -%TO.P,U13,G4*% -%TO.N,N/C*% X63953400Y73384800D03* -%TO.P,U13,G3*% X64953400Y73384800D03* -%TO.P,U13,G2*% X65953400Y73384800D03* -%TO.P,U13,G1*% X66953400Y73384800D03* -%TO.P,U13,F22*% -%TO.N,VCCO_3V3*% X45953400Y74384800D03* -%TO.P,U13,F21*% -%TO.N,N/C*% X46953400Y74384800D03* -%TO.P,U13,F20*% X47953400Y74384800D03* -%TO.P,U13,F19*% X48953400Y74384800D03* -%TO.P,U13,F18*% X49953400Y74384800D03* -%TO.P,U13,F17*% -%TO.N,GND*% X50953400Y74384800D03* -%TO.P,U13,F16*% -%TO.N,FPGA_IRQ_N_1*% X51953400Y74384800D03* -%TO.P,U13,F15*% -%TO.N,N/C*% X52953400Y74384800D03* -%TO.P,U13,F14*% -%TO.N,FPGA_IRQ_N_0*% X53953400Y74384800D03* -%TO.P,U13,F13*% -%TO.N,N/C*% X54953400Y74384800D03* -%TO.P,U13,F12*% -%TO.N,VCCO_3V3*% X55953400Y74384800D03* -%TO.P,U13,F11*% -%TO.N,GND*% X56953400Y74384800D03* -%TO.P,U13,F10*% -%TO.N,N/C*% X57953400Y74384800D03* -%TO.P,U13,F9*% X58953400Y74384800D03* -%TO.P,U13,F8*% X59953400Y74384800D03* -%TO.P,U13,F7*% X60953400Y74384800D03* -%TO.P,U13,F6*% X61953400Y74384800D03* -%TO.P,U13,F5*% -%TO.N,GND*% X62953400Y74384800D03* -%TO.P,U13,F4*% -%TO.N,N/C*% X63953400Y74384800D03* -%TO.P,U13,F3*% X64953400Y74384800D03* -%TO.P,U13,F2*% -%TO.N,VCCO_3V3*% X65953400Y74384800D03* -%TO.P,U13,F1*% -%TO.N,N/C*% X66953400Y74384800D03* -%TO.P,U13,E22*% X45953400Y75384800D03* -%TO.P,U13,E21*% X46953400Y75384800D03* -%TO.P,U13,E20*% -%TO.N,GND*% X47953400Y75384800D03* -%TO.P,U13,E19*% -%TO.N,N/C*% X48953400Y75384800D03* -%TO.P,U13,E18*% X49953400Y75384800D03* -%TO.P,U13,E17*% -%TO.N,FPGA_IRQ_N_2*% X50953400Y75384800D03* -%TO.P,U13,E16*% -%TO.N,N/C*% X51953400Y75384800D03* -%TO.P,U13,E15*% -%TO.N,VCCO_3V3*% X52953400Y75384800D03* -%TO.P,U13,E14*% -%TO.N,FPGA_GPIO_A_0*% X53953400Y75384800D03* -%TO.P,U13,E13*% -%TO.N,FPGA_GPIO_A_1*% X54953400Y75384800D03* -%TO.P,U13,E12*% -%TO.N,GND*% X55953400Y75384800D03* -%TO.P,U13,E11*% X56953400Y75384800D03* -%TO.P,U13,E10*% -%TO.N,N/C*% X57953400Y75384800D03* -%TO.P,U13,E9*% -%TO.N,GND*% X58953400Y75384800D03* -%TO.P,U13,E8*% -%TO.N,N/C*% X59953400Y75384800D03* -%TO.P,U13,E7*% -%TO.N,GND*% X60953400Y75384800D03* -%TO.P,U13,E6*% -%TO.N,N/C*% X61953400Y75384800D03* -%TO.P,U13,E5*% -%TO.N,GND*% X62953400Y75384800D03* -%TO.P,U13,E4*% X63953400Y75384800D03* -%TO.P,U13,E3*% -%TO.N,N/C*% X64953400Y75384800D03* -%TO.P,U13,E2*% X65953400Y75384800D03* -%TO.P,U13,E1*% X66953400Y75384800D03* -%TO.P,U13,D22*% X45953400Y76384800D03* -%TO.P,U13,D21*% X46953400Y76384800D03* -%TO.P,U13,D20*% X47953400Y76384800D03* -%TO.P,U13,D19*% X48953400Y76384800D03* -%TO.P,U13,D18*% -%TO.N,VCCO_3V3*% X49953400Y76384800D03* -%TO.P,U13,D17*% -%TO.N,FPGA_GCLK*% X50953400Y76384800D03* -%TO.P,U13,D16*% -%TO.N,N/C*% X51953400Y76384800D03* -%TO.P,U13,D15*% X52953400Y76384800D03* -%TO.P,U13,D14*% -%TO.N,FPGA_GPIO_B_3*% X53953400Y76384800D03* -%TO.P,U13,D13*% -%TO.N,GND*% X54953400Y76384800D03* -%TO.P,U13,D12*% X55953400Y76384800D03* -%TO.P,U13,D11*% -%TO.N,N/C*% X56953400Y76384800D03* -%TO.P,U13,D10*% X57953400Y76384800D03* -%TO.P,U13,D9*% X58953400Y76384800D03* -%TO.P,U13,D8*% -%TO.N,GND*% X59953400Y76384800D03* -%TO.P,U13,D7*% -%TO.N,N/C*% X60953400Y76384800D03* -%TO.P,U13,D6*% X61953400Y76384800D03* -%TO.P,U13,D5*% X62953400Y76384800D03* -%TO.P,U13,D4*% -%TO.N,GND*% X63953400Y76384800D03* -%TO.P,U13,D3*% X64953400Y76384800D03* -%TO.P,U13,D2*% -%TO.N,N/C*% X65953400Y76384800D03* -%TO.P,U13,D1*% X66953400Y76384800D03* -%TO.P,U13,C22*% -%TO.N,FPGA_GPIO_B_7*% X45953400Y77384800D03* -%TO.P,U13,C21*% -%TO.N,VCCO_3V3*% X46953400Y77384800D03* -%TO.P,U13,C20*% -%TO.N,FPGA_GPIO_B_6*% X47953400Y77384800D03* -%TO.P,U13,C19*% -%TO.N,N/C*% X48953400Y77384800D03* -%TO.P,U13,C18*% -%TO.N,FPGA_GPIO_B_4*% X49953400Y77384800D03* -%TO.P,U13,C17*% -%TO.N,N/C*% X50953400Y77384800D03* -%TO.P,U13,C16*% -%TO.N,GND*% X51953400Y77384800D03* -%TO.P,U13,C15*% -%TO.N,FPGA_GPIO_B_1*% X52953400Y77384800D03* -%TO.P,U13,C14*% -%TO.N,FPGA_IRQ_N_3*% X53953400Y77384800D03* -%TO.P,U13,C13*% -%TO.N,FPGA_GPIO_A_4*% X54953400Y77384800D03* -%TO.P,U13,C12*% -%TO.N,GND*% X55953400Y77384800D03* -%TO.P,U13,C11*% -%TO.N,N/C*% X56953400Y77384800D03* -%TO.P,U13,C10*% -%TO.N,GND*% X57953400Y77384800D03* -%TO.P,U13,C9*% -%TO.N,N/C*% X58953400Y77384800D03* -%TO.P,U13,C8*% X59953400Y77384800D03* -%TO.P,U13,C7*% X60953400Y77384800D03* -%TO.P,U13,C6*% -%TO.N,GND*% X61953400Y77384800D03* -%TO.P,U13,C5*% -%TO.N,N/C*% X62953400Y77384800D03* -%TO.P,U13,C4*% X63953400Y77384800D03* -%TO.P,U13,C3*% -%TO.N,GND*% X64953400Y77384800D03* -%TO.P,U13,C2*% -%TO.N,N/C*% X65953400Y77384800D03* -%TO.P,U13,C1*% -%TO.N,VCCO_3V3*% X66953400Y77384800D03* -%TO.P,U13,B22*% -%TO.N,N/C*% X45953400Y78384800D03* -%TO.P,U13,B21*% X46953400Y78384800D03* -%TO.P,U13,B20*% -%TO.N,AVR_GPIO_FPGA_0*% X47953400Y78384800D03* -%TO.P,U13,B19*% -%TO.N,GND*% X48953400Y78384800D03* -%TO.P,U13,B18*% -%TO.N,FPGA_ENTROPY_DISABLE*% X49953400Y78384800D03* -%TO.P,U13,B17*% -%TO.N,N/C*% X50953400Y78384800D03* -%TO.P,U13,B16*% -%TO.N,FPGA_GPIO_B_2*% X51953400Y78384800D03* -%TO.P,U13,B15*% -%TO.N,FPGA_GPIO_A_7*% X52953400Y78384800D03* -%TO.P,U13,B14*% -%TO.N,VCCO_3V3*% X53953400Y78384800D03* -%TO.P,U13,B13*% -%TO.N,FPGA_GPIO_A_5*% X54953400Y78384800D03* -%TO.P,U13,B12*% -%TO.N,GND*% X55953400Y78384800D03* -%TO.P,U13,B11*% -%TO.N,N/C*% X56953400Y78384800D03* -%TO.P,U13,B10*% X57953400Y78384800D03* -%TO.P,U13,B9*% X58953400Y78384800D03* -%TO.P,U13,B8*% X59953400Y78384800D03* -%TO.P,U13,B7*% X60953400Y78384800D03* -%TO.P,U13,B6*% X61953400Y78384800D03* -%TO.P,U13,B5*% X62953400Y78384800D03* -%TO.P,U13,B4*% X63953400Y78384800D03* -%TO.P,U13,B3*% -%TO.N,GND*% X64953400Y78384800D03* -%TO.P,U13,B2*% -%TO.N,N/C*% X65953400Y78384800D03* -%TO.P,U13,B1*% X66953400Y78384800D03* -%TO.P,U13,A22*% -%TO.N,GND*% X45953400Y79384800D03* -%TO.P,U13,A21*% -%TO.N,FPGA_GPIO_B_5*% X46953400Y79384800D03* -%TO.P,U13,A20*% -%TO.N,AVR_GPIO_FPGA_1*% X47953400Y79384800D03* -%TO.P,U13,A19*% -%TO.N,AVR_GPIO_FPGA_3*% X48953400Y79384800D03* -%TO.P,U13,A18*% -%TO.N,AVR_GPIO_FPGA_2*% X49953400Y79384800D03* -%TO.P,U13,A17*% -%TO.N,VCCO_3V3*% X50953400Y79384800D03* -%TO.P,U13,A16*% -%TO.N,FPGA_GPIO_B_0*% X51953400Y79384800D03* -%TO.P,U13,A15*% -%TO.N,FPGA_GPIO_A_6*% X52953400Y79384800D03* -%TO.P,U13,A14*% -%TO.N,FPGA_GPIO_A_3*% X53953400Y79384800D03* -%TO.P,U13,A13*% -%TO.N,FPGA_GPIO_A_2*% X54953400Y79384800D03* -%TO.P,U13,A12*% -%TO.N,GND*% X55953400Y79384800D03* -%TO.P,U13,A11*% X56953400Y79384800D03* -%TO.P,U13,A10*% -%TO.N,N/C*% X57953400Y79384800D03* -%TO.P,U13,A9*% -%TO.N,GND*% X58953400Y79384800D03* -%TO.P,U13,A8*% -%TO.N,N/C*% X59953400Y79384800D03* -%TO.P,U13,A7*% -%TO.N,GND*% X60953400Y79384800D03* -%TO.P,U13,A6*% -%TO.N,N/C*% X61953400Y79384800D03* -%TO.P,U13,A5*% -%TO.N,GND*% X62953400Y79384800D03* -%TO.P,U13,A4*% -%TO.N,N/C*% X63953400Y79384800D03* -%TO.P,U13,A3*% -%TO.N,GND*% X64953400Y79384800D03* -%TO.P,U13,A2*% X65953400Y79384800D03* -%TO.P,U13,A1*% -%TO.N,N/C*% X66953400Y79384800D03* -%TD*% D43* -%TO.P,U14,PAD39*% -%TO.N,GND*% X35458400Y75295600D03* D44* -%TO.P,U14,38*% -%TO.N,N/C*% X33553400Y79555600D03* -%TO.P,U14,37*% X33553400Y79055600D03* -%TO.P,U14,36*% X33553400Y78555600D03* -%TO.P,U14,35*% X33553400Y78055600D03* -%TO.P,U14,34*% X33553400Y77555600D03* -%TO.P,U14,33*% -%TO.N,VCC_5V0*% X33553400Y77055600D03* -%TO.P,U14,32*% -%TO.N,GND*% X33553400Y76555600D03* -%TO.P,U14,31*% -%TO.N,NetC117_2*% X33553400Y76047600D03* -%TO.P,U14,30*% -%TO.N,NetC115_1*% X33553400Y75539600D03* -%TO.P,U14,29*% -%TO.N,NetR53_2*% X33553400Y75031600D03* -%TO.P,U14,28*% -%TO.N,POK_VCCAUX*% X33553400Y74549000D03* -%TO.P,U14,27*% -%TO.N,PWR_ENA_VCCAUX*% X33553400Y74041000D03* -%TO.P,U14,26*% -%TO.N,NetR52_1*% X33553400Y73533000D03* D45* -%TO.P,U14,25*% -%TO.N,N/C*% X34188400Y73152000D03* -%TO.P,U14,24*% X34696400Y73152000D03* -%TO.P,U14,23*% X35204400Y73152000D03* -%TO.P,U14,22*% X35708400Y73152000D03* -%TO.P,U14,21*% -%TO.N,VCC_5V0*% X36208400Y73152000D03* -%TO.P,U14,20*% X36708400Y73152000D03* D44* -%TO.P,U14,19*% X37358400Y73533000D03* -%TO.P,U14,18*% -%TO.N,GND*% X37358400Y74041000D03* -%TO.P,U14,17*% X37358400Y74549000D03* -%TO.P,U14,16*% X37358400Y75031600D03* -%TO.P,U14,15*% X37358400Y75539600D03* -%TO.P,U14,14*% X37358400Y76047600D03* -%TO.P,U14,13*% X37358400Y76555600D03* -%TO.P,U14,12*% -%TO.N,N/C*% X37358400Y77055600D03* -%TO.P,U14,11*% -%TO.N,NetC117_1*% X37358400Y77555600D03* -%TO.P,U14,10*% X37358400Y78055600D03* -%TO.P,U14,9*% X37358400Y78555600D03* -%TO.P,U14,8*% X37358400Y79055600D03* -%TO.P,U14,7*% X37358400Y79555600D03* D45* -%TO.P,U14,6*% X36708400Y79955600D03* -%TO.P,U14,5*% X36208400Y79955600D03* -%TO.P,U14,4*% -%TO.N,N/C*% X35708400Y79955600D03* -%TO.P,U14,3*% X35204400Y79955600D03* -%TO.P,U14,2*% X34696400Y79955600D03* -%TO.P,U14,1*% X34188400Y79955600D03* -%TD*% -%TO.P,U15,1*% -%TO.N,N/C*% X12115800Y37697200D03* -%TO.P,U15,2*% X11607800Y37697200D03* -%TO.P,U15,3*% X11099800Y37697200D03* -%TO.P,U15,4*% X10595800Y37697200D03* -%TO.P,U15,5*% -%TO.N,NetC118_1*% X10095800Y37697200D03* -%TO.P,U15,6*% X9595800Y37697200D03* D44* -%TO.P,U15,7*% X8945800Y38097200D03* -%TO.P,U15,8*% X8945800Y38597200D03* -%TO.P,U15,9*% X8945800Y39097200D03* -%TO.P,U15,10*% X8945800Y39597200D03* -%TO.P,U15,11*% X8945800Y40097200D03* -%TO.P,U15,12*% -%TO.N,N/C*% X8945800Y40597200D03* -%TO.P,U15,13*% -%TO.N,GND*% X8945800Y41097200D03* -%TO.P,U15,14*% X8945800Y41605200D03* -%TO.P,U15,15*% X8945800Y42113200D03* -%TO.P,U15,16*% X8945800Y42621200D03* -%TO.P,U15,17*% X8945800Y43103800D03* -%TO.P,U15,18*% X8945800Y43611800D03* -%TO.P,U15,19*% -%TO.N,VCC_5V0*% X8945800Y44119800D03* D45* -%TO.P,U15,20*% X9595800Y44500800D03* -%TO.P,U15,21*% X10095800Y44500800D03* -%TO.P,U15,22*% -%TO.N,N/C*% X10595800Y44500800D03* -%TO.P,U15,23*% X11099800Y44500800D03* -%TO.P,U15,24*% X11607800Y44500800D03* -%TO.P,U15,25*% X12115800Y44500800D03* D44* -%TO.P,U15,26*% -%TO.N,NetR54_1*% X12750800Y44119800D03* -%TO.P,U15,27*% -%TO.N,PWR_ENA_VCCO*% X12750800Y43611800D03* -%TO.P,U15,28*% -%TO.N,POK_VCCO*% X12750800Y43103800D03* -%TO.P,U15,29*% -%TO.N,NetR55_2*% X12750800Y42621200D03* -%TO.P,U15,30*% -%TO.N,NetC116_1*% X12750800Y42113200D03* -%TO.P,U15,31*% -%TO.N,NetC118_2*% X12750800Y41605200D03* -%TO.P,U15,32*% -%TO.N,GND*% X12750800Y41097200D03* -%TO.P,U15,33*% -%TO.N,VCC_5V0*% X12750800Y40597200D03* -%TO.P,U15,34*% -%TO.N,N/C*% X12750800Y40097200D03* -%TO.P,U15,35*% X12750800Y39597200D03* -%TO.P,U15,36*% X12750800Y39097200D03* -%TO.P,U15,37*% X12750800Y38597200D03* -%TO.P,U15,38*% X12750800Y38097200D03* D43* -%TO.P,U15,PAD39*% -%TO.N,GND*% X10845800Y42357200D03* -%TD*% D44* -%TO.P,U16,1*% -%TO.N,GND*% X31484200Y60985400D03* -%TO.P,U16,2*% X31484200Y60502800D03* -%TO.P,U16,3*% X31484200Y59994800D03* -%TO.P,U16,4*% X31484200Y59486800D03* -%TO.P,U16,5*% -%TO.N,NetC208_1*% X31484200Y59004200D03* -%TO.P,U16,6*% X31484200Y58496200D03* -%TO.P,U16,7*% X31484200Y57988200D03* -%TO.P,U16,8*% X31484200Y57480200D03* -%TO.P,U16,9*% X31484200Y56980200D03* -%TO.P,U16,10*% X31484200Y56480200D03* -%TO.P,U16,11*% X31484200Y55980200D03* -%TO.P,U16,12*% X31484200Y55480200D03* -%TO.P,U16,13*% X31484200Y54980200D03* -%TO.P,U16,14*% -%TO.N,N/C*% X31484200Y54480200D03* -%TO.P,U16,15*% X31484200Y53980200D03* D45* -%TO.P,U16,16*% X30484200Y53580200D03* -%TO.P,U16,17*% X29984200Y53580200D03* -%TO.P,U16,18*% X29484200Y53580200D03* -%TO.P,U16,19*% X28984200Y53580200D03* -%TO.P,U16,20*% X28484200Y53580200D03* -%TO.P,U16,21*% X27984200Y53580200D03* -%TO.P,U16,22*% X27484200Y53580200D03* -%TO.P,U16,23*% X26984200Y53580200D03* -%TO.P,U16,24*% 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X20472400Y60502800D03* -%TO.P,U16,49*% X20472400Y60985400D03* D45* -%TO.P,U16,50*% X21463000Y61391800D03* -%TO.P,U16,51*% -%TO.N,NetR66_1*% X21971000Y61391800D03* -%TO.P,U16,52*% -%TO.N,PWR_ENA_VCCINT*% X22479000Y61391800D03* -%TO.P,U16,53*% -%TO.N,VCC_5V0*% X22961600Y61391800D03* -%TO.P,U16,54*% -%TO.N,POK_VCCINT*% X23469600Y61391800D03* -%TO.P,U16,55*% -%TO.N,GND*% X23977600Y61391800D03* -%TO.P,U16,56*% -%TO.N,NetC208_2*% X24460200Y61391800D03* -%TO.P,U16,57*% -%TO.N,N/C*% X24968200Y61391800D03* -%TO.P,U16,58*% X25476200Y61391800D03* -%TO.P,U16,59*% -%TO.N,NetC207_1*% X25984200Y61391800D03* -%TO.P,U16,60*% -%TO.N,N/C*% X26484200Y61391800D03* -%TO.P,U16,61*% X26984200Y61391800D03* -%TO.P,U16,62*% X27484200Y61391800D03* -%TO.P,U16,63*% -%TO.N,NetR67_1*% X27984200Y61391800D03* -%TO.P,U16,64*% -%TO.N,GND*% X28484200Y61391800D03* -%TO.P,U16,65*% X28984200Y61391800D03* -%TO.P,U16,66*% X29484200Y61391800D03* -%TO.P,U16,67*% X29984200Y61391800D03* -%TO.P,U16,68*% X30484200Y61391800D03* D46* -%TO.P,U16,PAD69*% X23809200Y56855200D03* D47* -%TO.P,U16,PAD70*% X29534200Y60130200D03* -%TD*% D48* -%TO.P,,*% -%TO.N,*% X96143740Y8093820D03* -%TO.N,GND*% X7901500Y67272080D03* -%TO.N,*% X9991720Y2518470D03* X43039280Y54557750D03* X71321220Y80167810D03* X63284800Y47850000D03* X33950020Y17890480D03* -%TD*% D49* -%TO.N,FPGA_DONE_INT*% X84500000Y-6500000D03* -%TO.N,NetLED18_2*% -X86500000Y-6500000D03* -%TO.N,NetLED18_1*% -X85500000Y-6500000D03* -%TO.N,NetLED13_1*% -X83500000Y-6500000D03* -%TO.N,FPGA_DONE_INT*% X72725000Y-16500000D03* -%TO.N,NetLED18_2*% -X77496220Y-16469460D03* -%TO.N,NetLED18_1*% -X77496220Y-14963590D03* -%TO.N,NetLED13_1*% +X83500000Y-6500000D03* X72750000Y-15000000D03* -%TO.N,GND*% +X85500000Y-6500000D03* +X77496220Y-14963590D03* +X86500000Y-6500000D03* +X77496220Y-16469460D03* X66000000Y5500000D03* -D50* +D48* X60660000Y-14963590D03* X80500000Y-9536420D03* X89500000Y-15000000D03* @@ -4206,33 +1621,6 @@ X69488400Y-9000000D03* X60500000Y-9413610D03* X85000000Y-8000000D03* X66500000Y-9000000D03* -D49* -%TO.N,NetLED3_1*% -X39500000Y-14250000D03* -%TO.N,NetLED15_1*% -X56000000Y-14250000D03* -%TO.N,NetLED16_1*% -X54000000Y-14250000D03* -%TO.N,NetLED14_1*% -X52000000Y-14250000D03* -%TO.N,NetLED17_1*% -X50000000Y-14250000D03* -%TO.N,NetLED1_1*% -X45500000Y-14250000D03* -%TO.N,NetLED4_1*% -X43500000Y-14250000D03* -%TO.N,NetLED2_1*% -X41500000Y-14250000D03* -%TO.N,NetLED9_1*% -X34250000Y-14250000D03* -%TO.N,NetLED12_1*% -X32250000Y-14250000D03* -%TO.N,NetLED10_1*% -X30255000Y-14250000D03* -%TO.N,NetLED11_1*% -X28250000Y-14250000D03* -D50* -%TO.N,GND*% X35750000Y-16750000D03* X57500000Y-16800000D03* X48750000Y-16750000D03* @@ -4240,28 +1628,52 @@ X47000000Y-16750000D03* X37982000Y-16750000D03* X27000000Y-16800000D03* D49* -%TO.N,AVR_GPIO_4*% +X30530800Y-9000000D03* +X30750000Y-1500000D03* +X8250000Y2654120D03* +X11772170Y2692730D03* +D48* +X43593770Y52492120D03* +D49* +X84554130Y15100740D03* +X87550000Y15025000D03* +X88679330Y15000730D03* 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-X38650000Y25150000D03* -X45925000Y31650000D03* -X30026470Y9425460D03* -%TO.N,AVR_LED3*% -X29238280Y9450000D03* -%TO.N,AVR_GPIO_1*% -X54125000Y35950000D03* -%TO.N,AVR_GPIO_0*% -X53925000Y36600000D03* -%TO.N,ARM_FPGA_CFG_CS_N*% -X48500000Y34425000D03* -%TO.N,3V3_BATT*% -X47025000Y36050000D03* -%TO.N,AVR_LED4*% -X55452710Y19425950D03* -%TO.N,AVR_GPIO_4*% -X52675000Y21200000D03* -%TO.N,AVR_LED4*% -X44250000Y16550000D03* -%TO.N,MKM_AVR_CS_N*% -X69575000Y27000000D03* -%TO.N,GND*% -X69113400Y12736600D03* -X51436900Y77889100D03* -D50* -X46125000Y85949990D03* -%TO.N,VCCO_3V3*% -X43750000Y87525000D03* -%TO.N,GND*% -X40950000Y87500000D03* -%TO.N,VCCO_3V3*% -X45125000Y86700080D03* -%TO.N,GND*% -X47175000Y87350000D03* -X48700000Y87325000D03* -D49* -%TO.N,FPGA_ENTROPY_DISABLE*% -X49455700Y78905100D03* -%TO.N,FPGA_GPIO_A_7*% -X52452900Y78905100D03* -%TO.N,FPGA_GPIO_A_6*% -X52452900Y79895700D03* -%TO.N,FPGA_GPIO_B_2*% -X51436900Y78905100D03* -%TO.N,FPGA_GPIO_B_1*% -X52452900Y77889100D03* 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-X48439700Y63889500D03* -%TO.N,*% X61448700Y76898500D03* -%TO.N,FMC_NOE*% -X51436900Y60889500D03* -%TO.N,*% X64448700Y73901300D03* -%TO.N,VCCO_3V3*% -X48439700Y73901300D03* -%TO.N,*% X47449100Y71894700D03* X47449100Y65889500D03* X59448700Y77889100D03* -%TO.N,FMC_A11*% -X53443500Y59889500D03* -%TO.N,VCCO_3V3*% -X65448700Y71894700D03* -%TO.N,*% X59453420Y59884770D03* -%TO.N,GND*% -X65453430Y65884780D03* -%TO.N,*% X49455700Y75882500D03* X47449100Y72885300D03* -%TO.N,FMC_D29*% -X49455700Y61889500D03* -%TO.N,GND*% -X63448700Y75882500D03* -X47449100Y64889500D03* -%TO.N,*% X60448700Y77889100D03* -%TO.N,GND*% -X52452900Y59889500D03* -%TO.N,*% X65448700Y72885300D03* X60453420Y59884770D03* X65453430Y64884770D03* -%TO.N,FMC_NE1*% -X63453420Y61884780D03* -%TO.N,FMC_NL*% -X50446300Y60889500D03* -%TO.N,*% X64448700Y74891900D03* X62453420Y60884780D03* -%TO.N,GND*% -X64453420Y62884780D03* -%TO.N,*% X48439700Y74891900D03* -%TO.N,FPGA_GCLK*% -X50446300Y76898500D03* -%TO.N,VCCO_3V3*% -X48439700Y62889500D03* -%TO.N,*% X62448700Y76898500D03* -%TO.N,GND*% -X55445380Y58884780D03* -X66453420Y69892820D03* -%TO.N,*% X66453420Y67884780D03* -%TO.N,GND*% -X55450100Y78905100D03* -%TO.N,*% X46433100Y67889500D03* X57448700Y78905100D03* X47449100Y63889500D03* @@ -4964,386 +1823,259 @@ X61448700Y77889100D03* X47449100Y73901300D03* X58453420Y58884780D03* X66453420Y66884780D03* -%TO.N,FMC_A5*% -X54434100Y58889500D03* -%TO.N,*% X66448700Y70904100D03* -%TO.N,FMC_A18*% -X61453430Y59884770D03* -%TO.N,*% X65453430Y63884770D03* -%TO.N,FMC_A3*% -X51436900Y59889500D03* -%TO.N,*% X65448700Y73901300D03* -%TO.N,VCCO_3V3*% -X46433100Y66889500D03* -%TO.N,*% X58448700Y78905100D03* X46433100Y70904100D03* -%TO.N,FPGA_GPIO_A_5*% -X54434100Y78905100D03* -%TO.N,FMC_A10*% -X53443500Y58889500D03* -%TO.N,*% X66448700Y71894700D03* -%TO.N,FMC_A16*% -X59453420Y58884780D03* -%TO.N,*% X66453420Y65884780D03* X46433100Y71894700D03* -%TO.N,VCCO_3V3*% -X53443500Y78905100D03* -%TO.N,FMC_D31*% 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-X26450000Y16400000D03* -X20638600Y13336400D03* -%TO.N,VCCO_3V3*% -X80695800Y80725000D03* -%TO.N,15V_STABLE*% -X92207800Y84632800D03* -%TO.N,GND*% X73500000Y95250000D03* X73500000Y90000000D03* X73500000Y88000000D03* @@ -6108,27 +2322,17 @@ X94000000Y95250000D03* X94000000Y90000000D03* X94000000Y88000000D03* X87000000Y96250000D03* -%TO.N,15V_LDO_ENABLE*% -X70500000Y91250000D03* -%TO.N,PWR_18V*% -X70500000Y88000000D03* -%TO.N,GND*% X70250000Y92500000D03* X70250000Y98250000D03* X70750000Y96338800D03* X71500000Y85250000D03* X71500000Y84000000D03* -%TO.N,NetR3_2*% -X24250000Y80750000D03* -%TO.N,PWR_18V*% -X24700000Y84700000D03* -%TO.N,GND*% X27200000Y84700000D03* X27500000Y78100000D03* X26831200Y71831200D03* X28194000Y71431000D03* X26050000Y74900000D03* -D50* +D48* X25525000Y79000000D03* X31525000Y82500000D03* X32000000Y94000000D03* @@ -6139,501 +2343,81 @@ X35375000Y81625000D03* X30169400Y76344400D03* X31580600Y76344400D03* X30200000Y77300000D03* -%TO.N,VCC_5V0*% -X37125000Y71750000D03* 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X31550000Y63475000D03* -D49* -%TO.N,FPGA_IRQ_N_2*% -X52950000Y19675000D03* -%TO.N,FT_TXD*% -X18025000Y17650000D03* -%TO.N,RTC_SDA*% -X26801310Y41552030D03* -%TO.N,VCCO_3V3*% -X31850000Y43975000D03* -X32175000Y42675000D03* -%TO.N,RTC_SCL*% -X26950000Y42800000D03* -%TO.N,RTC_MFP*% -X26825000Y44225000D03* -%TO.N,NRST*% -X32000000Y37000000D03* -%TO.N,SWDCLK*% -X60125000Y19500000D03* -%TO.N,SWDIO*% -X61450000Y24600000D03* -%TO.N,FMC_D23*% -X62003030Y21576050D03* -%TO.N,FT_CTS*% -X15050000Y14900000D03* -X38050000Y41400000D03* -X24575000Y38700000D03* -%TO.N,FT_RTS*% -X38100000Y40550000D03* -X25275000Y37975000D03* -%TO.N,FT_VCC3V3*% -X39550000Y4800000D03* -%TO.N,FMC_D3*% -X71675000Y39275000D03* -%TO.N,FMC_NWAIT*% -X66175000Y38200000D03* -%TO.N,FMC_A10*% -X69275000Y48425000D03* -D50* -%TO.N,GND*% X70800000Y53025000D03* D49* -%TO.N,KSM_PROM_MISO*% -X31750000Y51625000D03* -%TO.N,GND*% X35925000Y59100000D03* -D50* +D48* X34425000Y52400000D03* -D49* -%TO.N,FPGA_DONE*% -X50250000Y20900000D03* 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-%TO.N,FMC_SDCKE0*% -X42150000Y38425000D03* -%TO.N,ARM_FPGA_CFG_SCLK*% -X42025000Y37425000D03* -X61850000Y37250000D03* -%TO.N,ARM_FPGA_CFG_MOSI*% -X64800000Y44350000D03* -%TO.N,FMC_A18*% -X64553150Y42025000D03* -%TO.N,FMC_A12*% -X61450000Y34300000D03* -%TO.N,ARM_FPGA_CFG_MOSI*% -X61975000Y35600000D03* -%TO.N,3V3_BATT*% -X65350000Y33525000D03* -%TO.N,FT_MGMT_TXD1*% -X90600000Y14525000D03* -%TO.N,MKM_MOSI*% -X73538600Y23825000D03* -X75600000Y33625000D03* -%TO.N,FMC_D15*% -X76900000Y37425000D03* -%TO.N,MKM_SCK*% -X73950000Y37175000D03* -X75996800Y24175000D03* -%TO.N,GND*% X80125000Y29750000D03* X82346800Y32003200D03* -%TO.N,MKM_CONTROL_FPGA_DIS*% -X69675000Y33775000D03* -%TO.N,GND*% X68264800Y30810200D03* X71100000Y31975000D03* X71625000Y29750000D03* X73050000Y29800000D03* -%TO.N,3V3_BATT*% -X71425000Y37075000D03* -%TO.N,AVR_GPIO_7*% -X57300000Y21400000D03* -%TO.N,AVR_GPIO_6*% -X56825000Y21925000D03* -%TO.N,AVR_GPIO_5*% -X56050000Y22150000D03* -%TO.N,FPGA_GPIO_LED_3*% -X51900000Y20850000D03* -X77975000Y7550000D03* -%TO.N,FT_MGMT_DTR*% -X86225000Y20075000D03* -%TO.N,MKM_CONTROL_AVR_ENA*% -X69425000Y28025000D03* -%TO.N,FT_MGMT_CTS*% -X85400000Y19775000D03* -%TO.N,FT_MGMT_RTS*% -X84600000Y20050000D03* -%TO.N,FT_MGMT_RXD*% -X93108400Y17433400D03* -%TO.N,FT_MGMT_TXD*% -X93800000Y15125000D03* -%TO.N,FMC_D24*% -X61925000Y23600000D03* -%TO.N,AVR_LED4*% -X57975000Y29350000D03* -%TO.N,AVR_PANIC*% -X57777820Y28551390D03* -%TO.N,FMC_D3*% -X58900000Y26050000D03* -%TO.N,FMC_D2*% -X59475000Y26725000D03* -%TO.N,MKM_AVR_CS_N*% -X58275000Y28129350D03* -%TO.N,AVR_LED4*% -X26876310Y8025390D03* -%TO.N,FPGA_PROM_SCLK*% -X49475000Y32650000D03* -%TO.N,MKM_AVR_MOSI*% -X53700000Y37275000D03* -%TO.N,MKM_AVR_MISO*% -X52775000Y37300000D03* -%TO.N,AVR_RESET*% -X51925000Y37300000D03* -%TO.N,MKM_AVR_SCK*% -X51050000Y37275000D03* -%TO.N,AVR_LED3*% -X55500000Y36950000D03* -%TO.N,AVR_LED2*% -X56000000Y36425000D03* -%TO.N,AVR_LED1*% -X24000000Y9200000D03* -X30276480Y19475950D03* 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