From 3c347aee80c71f448e4cd625bd54d4552cafb912 Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Tue, 26 Sep 2017 10:07:53 +0200 Subject: init --- make-wrl-files.sh | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100755 make-wrl-files.sh (limited to 'make-wrl-files.sh') diff --git a/make-wrl-files.sh b/make-wrl-files.sh new file mode 100755 index 0000000..f1d264d --- /dev/null +++ b/make-wrl-files.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -e +set -x + +basepath=$(dirname $(readlink -e $0)) +start=${PWD} +for d in *-PcbLib *-PcbDoc; do + ( + test -d "${d}/Root Entry/Models" && cd "${d}/Root Entry/Models" + test -d "${d}/Root Entry/Library/Models" && cd "${d}/Root Entry/Library/Models" + echo "Converting STEP files in ${PWD}..." + freecad ${basepath}/altium2kicad/step2wrl.FCMacro || true + ) +done + +# converting all the step files takes time and is interactive, so cache the result +find . -name '*.wrl' -print0 | xargs -0 tar zcvf ${basepath}/wrl-files.tar.gz -- cgit v1.2.3