From 0900cae0efc7485fbf92480588e1835cbe4353b2 Mon Sep 17 00:00:00 2001
From: Fredrik Thulin <fredrik@thulin.net>
Date: Tue, 24 Apr 2018 10:58:05 +0200
Subject: ERC fixes

---
 fix-pcb.py | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

(limited to 'fix-pcb.py')

diff --git a/fix-pcb.py b/fix-pcb.py
index 52dc67f..3f0b0c8 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -15,7 +15,7 @@ def remove_tracks(board, layer):
     in KiCAD.
     """
     for this in [x for x in board.GetTracks() if x.GetLayerName() == layer]:
-        print('Removing track {} on Layer 4'.format(this))
+        print('Removing track {} on {}'.format(this, layer))
         board.Delete(this)
 
 #def set_tracks_width(board, layer, width):
@@ -111,7 +111,6 @@ def show_via_widths(board):
 
 
 def change_netclass_drill_size(board, from_, to_):
-    #help(board.GetDesignSettings())
     names = board.GetAllNetClasses()
     for name, net in names.iterator():
         if net.GetViaDrill() == pcbnew.FromMM(from_):
@@ -258,11 +257,26 @@ def fix_layer_B_aka_GBL(board):
     layer_zone_fixes(board, 'B.Cu', gnd_clearance=0.15)
 
 
+def fix_layer_Dwgs_User(board):
+    """
+    The Dwgs.User layer has three extra pin-1 marking for the ARM and the two SDRAM chips,
+    as well as chip outlines for the same chips as 'segments'. KiCad gets confused by this
+    and doesn't render the segments (probably since they are copper on a non-copper layer).
+
+    They cause ERC warnings so we remove them.
+    """
+    for this in [x for x in board.GetDrawings() if x.GetLayerName() == 'Dwgs.User']:
+        print("Removing drawing on Dwgs.User: {}".format(this))
+        board.Delete(this)
+    remove_tracks(board, 'Dwgs.User')
+
+
 def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alpha.kicad_pcb'):
     board = pcbnew.LoadBoard(in_fn)
     # normalize contents to be able to use diff to show changes made
     pcbnew.SaveBoard(in_fn + '.before-fix-pcb', board)
 
+    # Copper layers
     fix_layer_F_aka_GTL(board)
     fix_layer_In1_aka_GP1(board)
     fix_layer_In2_aka_G1(board)
@@ -271,6 +285,8 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp
     fix_layer_In5_aka_G2(board)
     fix_layer_In6_aka_GP4(board)
     fix_layer_B_aka_GBL(board)
+    # Non-copper layers
+    fix_layer_Dwgs_User(board)
 
     change_via_drill_size(board, 1.0, 0.5)
     # Changing these via widths minimizes diff on layer In1/GP1, but creates diff on
-- 
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