From 42b9a1ccc1061128b421427f484b33b33ef44d7f Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Mon, 23 Apr 2018 14:51:06 +0200 Subject: Use pcbnew.FromMM throughout. --- fix-pcb.py | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/fix-pcb.py b/fix-pcb.py index fdd1ec3..83f0136 100755 --- a/fix-pcb.py +++ b/fix-pcb.py @@ -54,23 +54,23 @@ def layer_zone_fixes(board, layer, clearance=0.15, min_width=0.05, thermal=0.5, continue print('Area {} {}'.format(area, area.GetNetname())) if area.GetNetname() == 'GND': - area.SetZoneClearance(int(gnd_clearance * 1000000)) - area.SetMinThickness(int(gnd_min_width * 1000000)) + area.SetZoneClearance(pcbnew.FromMM(gnd_clearance)) + area.SetMinThickness(pcbnew.FromMM(gnd_min_width)) # 0.25 clearance on the 'background' GND zone keeps the distance to the island # zones in the bottom half of layer 4, matching the clearance between the areas # but creating a bit more clearance around vias in KiCAD plot than in Altium - area.SetThermalReliefCopperBridge(int(gnd_thermal * 1000000)) + area.SetThermalReliefCopperBridge(pcbnew.FromMM(gnd_thermal)) area.SetPriority(gnd_priority) else: # 0.25 works better for the distance between zones in the bottom half of layer 4, # but does not allow copper between the vias under the FPGA # # Values below 0.15 or somewhere there does not seem to make a difference at all - area.SetZoneClearance(int(clearance * 1000000)) + area.SetZoneClearance(pcbnew.FromMM(clearance)) # This makes sharp edges matching Altium Designer # 0.0255 is the minimum KiCad wants in order to allow changes to the zone inside KiCad - area.SetMinThickness(int(min_width * 1000000)) - area.SetThermalReliefCopperBridge(int(thermal * 1000000)) + area.SetMinThickness(pcbnew.FromMM(min_width)) + area.SetThermalReliefCopperBridge(pcbnew.FromMM(thermal)) def change_via_drill_size(board, from_size, to_drill): @@ -81,6 +81,7 @@ def change_via_drill_size(board, from_size, to_drill): to not inherit the default for the net class which will be 0.25 mm. """ sizes = {} + from_size = pcbnew.FromMM(from_size) for this in board.GetTracks(): if type(this) is pcbnew.VIA: size = this.GetWidth() @@ -96,9 +97,9 @@ def change_netclass_drill_size(board, from_, to_): #help(board.GetDesignSettings()) names = board.GetAllNetClasses() for name, net in names.iterator(): - if net.GetViaDrill() == int(from_ * 1000000): - print("Netclass {} has drill size {}, changing to {}".format(name, net.GetViaDrill(), int(to_ * 1000000))) - net.SetViaDrill(int(to_ * 1000000)) + if net.GetViaDrill() == pcbnew.FromMM(from_): + print("Netclass {} has drill size {}, changing to {}".format(name, net.GetViaDrill(), pcbnew.FromMM(to_))) + net.SetViaDrill(pcbnew.FromMM(to_)) # @@ -242,7 +243,7 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp fix_layer_In6_aka_GP4(board) fix_layer_B_aka_GBL(board) - change_via_drill_size(board, 1000000, 0.5) + change_via_drill_size(board, 1.0, 0.5) change_netclass_drill_size(board, 0.635, 0.250) # Only show a single layer while working on this -- cgit v1.2.3