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path: root/rev03-KiCad/Cryptech Alpha.kicad_pcb
AgeCommit message (Collapse)Author
2018-05-21sync from schematicFredrik Thulin
2018-05-21update PCB from schematics (using F8)Fredrik Thulin
2018-05-21change default named nets to match what a schematic update wants to turn ↵Fredrik Thulin
them into
2018-05-21PCB footprint path fixesFredrik Thulin
2018-05-09newer KiCad-nightly seems to order vias after net numberFredrik Thulin
2018-04-26change segments to gr_line on non-copper layer Eco2.UserFredrik Thulin
2018-04-25simplify symbol library setupFredrik Thulin
2018-04-24ERC fixesFredrik Thulin
2018-04-23tune clearancesFredrik Thulin
2018-04-19Fix the drill size of the 296 0.5 mm holesFredrik Thulin
2018-04-19commit changes from updated altium2kicadFredrik Thulin
2017-09-27move all footprint descriptions from F.Silk to Cmts.UserFredrik Thulin
2017-09-27fix schematic component positions in KiCAD-nightlyFredrik Thulin
2017-09-26wrl shape workFredrik Thulin
2017-09-26loads of updatesFredrik Thulin
2017-09-22new attempt with updated upstream tool (still a lot of local changes)Fredrik Thulin
2016-12-11fix bad merge, and add block diagram as top sheetFredrik Thulin
2016-11-01mergeFredrik Thulin
2016-10-21many ratsnest fixes, and combine all libraries to oneFredrik Thulin
2016-10-20filled all zonesFredrik Thulin
2016-10-20don't do micro vias, apparently they are only between outer layer and the ↵Fredrik Thulin
one next to it
2016-10-20via size and micro fixupsFredrik Thulin
2016-10-20fixed some throughholes to be on layers *.Cu instead of just front and backFredrik Thulin
2016-10-19remove the test text againFredrik Thulin
2016-10-19saved using kicad, text label addedFredrik Thulin
2016-10-15initFredrik Thulin