diff options
Diffstat (limited to 'rev03-KiCad/rev02_13.sch')
| -rw-r--r-- | rev03-KiCad/rev02_13.sch | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/rev03-KiCad/rev02_13.sch b/rev03-KiCad/rev02_13.sch index 7ad0c66..5219803 100644 --- a/rev03-KiCad/rev02_13.sch +++ b/rev03-KiCad/rev02_13.sch @@ -294,23 +294,23 @@ Connection ~ 2400 4800 Connection ~ 2400 4900 Wire Wire Line 3400 5700 2000 5700 -Text Label 2900 5700 0 48 ~ +Text Label 3400 5700 2 48 ~ 0 FPGA_M2 Wire Wire Line 1500 9000 1500 9200 Wire Wire Line 1500 9000 900 9000 -Text Label 1000 9000 0 48 ~ +Text Label 900 9000 0 48 ~ 0 FPGA_M2 Wire Wire Line 3400 5800 2000 5800 -Text Label 2900 5800 0 48 ~ +Text Label 3400 5800 2 48 ~ 0 FPGA_JTAG_TCK Text Label 8430 8500 0 48 ~ FPGA_JTAG_TCK Wire Wire Line 3400 5900 2000 5900 -Text Label 2900 5900 0 48 ~ +Text Label 3400 5900 2 48 ~ 0 FPGA_JTAG_TDI Wire Wire Line 9000 8700 8800 8700 @@ -322,7 +322,7 @@ Text Label 8430 8700 0 48 ~ FPGA_JTAG_TDI Wire Wire Line 3400 6000 2000 6000 -Text Label 2900 6000 0 48 ~ +Text Label 3400 6000 2 48 ~ 0 FPGA_JTAG_TDO Wire Wire Line 9300 8800 8430 8800 @@ -330,7 +330,7 @@ Text Label 8430 8800 0 48 ~ FPGA_JTAG_TDO Wire Wire Line 3400 6100 2000 6100 -Text Label 2900 6100 0 48 ~ +Text Label 3400 6100 2 48 ~ 0 FPGA_JTAG_TMS Wire Wire Line 9100 8600 8900 8600 @@ -344,15 +344,15 @@ Wire Wire Line 6200 4900 6200 5100 Wire Wire Line 7600 5100 6200 5100 -Text Label 7010 5100 0 48 ~ +Text GLabel 7600 5100 2 48 Input ~ 0 FPGA_PROGRAM_B Wire Wire Line 3940 5300 3240 5300 -Text Label 3340 5300 0 48 ~ +Text GLabel 3940 5300 2 48 Input ~ 0 FPGA_PROGRAM_B Wire Wire Line 3400 5100 2000 5100 -Text Label 2900 5100 0 48 ~ +Text Label 3400 5100 2 48 ~ 0 FPGA_DONE_INT Wire Wire Line 4700 9400 4700 9500 @@ -365,23 +365,23 @@ FPGA_DONE_INT Connection ~ 4700 9500 Wire Wire Line 3400 5500 2000 5500 -Text Label 2900 5500 0 48 ~ +Text Label 3400 5500 2 48 ~ 0 FPGA_M0 Wire Wire Line 3100 9000 2500 9000 Wire Wire Line 3100 8800 3100 9000 -Text Label 2600 9000 0 48 ~ +Text Label 2500 9000 0 48 ~ 0 FPGA_M0 Wire Wire Line 3400 5600 2000 5600 -Text Label 2900 5600 0 48 ~ +Text Label 3400 5600 2 48 ~ 0 FPGA_M1 Wire Wire Line 2300 9000 1700 9000 Wire Wire Line 2300 9000 2300 9200 -Text Label 1750 9000 0 48 ~ +Text Label 1700 9000 0 48 ~ 0 FPGA_M1 Wire Wire Line 5800 4900 5800 5400 @@ -394,7 +394,7 @@ FPGA_INIT_B_INT Connection ~ 5800 5400 Wire Wire Line 3940 5200 3240 5200 -Text Label 3340 5200 0 48 ~ +Text Label 3940 5200 2 48 ~ 0 FPGA_INIT_B_INT Wire Wire Line 6600 5600 6400 5600 @@ -402,18 +402,18 @@ Wire Wire Line 6600 5600 6600 5800 Wire Wire Line 7600 5600 6600 5600 -Text Label 7130 5600 0 48 ~ +Text GLabel 7600 5600 2 48 BiDi ~ 0 FPGA_INIT_B Connection ~ 6600 5600 Wire Wire Line 4700 8900 4700 9100 Wire Wire Line 5700 9500 5400 9500 -Text Label 5400 9500 0 48 ~ +Text GLabel 5700 9500 2 48 Output ~ 0 FPGA_DONE Wire Wire Line 3940 5400 3240 5400 -Text Label 3340 5400 0 48 ~ +Text GLabel 3940 5400 2 48 Output ~ 0 FPGA_CFG_SCLK Wire Wire Line 2840 5200 2000 5200 |