diff options
Diffstat (limited to 'rev03-KiCad/Cryptech Alpha.kicad_pcb')
| -rw-r--r-- | rev03-KiCad/Cryptech Alpha.kicad_pcb | 55 |
1 files changed, 25 insertions, 30 deletions
diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb index 47d0359..155ef73 100644 --- a/rev03-KiCad/Cryptech Alpha.kicad_pcb +++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb @@ -3,7 +3,7 @@ (general (thickness 1.6) (drawings 6665) - (tracks 9210) + (tracks 9205) (zones 0) (modules 386) (nets 304) @@ -41,7 +41,7 @@ (setup (last_trace_width 0.254) - (trace_clearance 0.15) + (trace_clearance 0.125) (zone_clearance 0.0144) (zone_45_only no) (trace_min 0.15) @@ -401,7 +401,7 @@ (net 303 VCCO_3V3) (net_class Default "This is the default net class." - (clearance 0.15) + (clearance 0.125) (trace_width 0.254) (via_dia 0.889) (via_drill 0.25) @@ -613,7 +613,7 @@ ) (net_class Default "This is the default net class." - (clearance 0.15) + (clearance 0.125) (trace_width 0.254) (via_dia 0.889) (via_drill 0.25) @@ -825,7 +825,7 @@ ) (net_class FMC FMC - (clearance 0.15) + (clearance 0.125) (trace_width 0.254) (via_dia 0.889) (via_drill 0.25) @@ -910,7 +910,7 @@ ) (net_class FPGA_GPIO FPGA_GPIO - (clearance 0.15) + (clearance 0.125) (trace_width 0.254) (via_dia 0.889) (via_drill 0.25) @@ -935,7 +935,7 @@ ) (net_class USB USB - (clearance 0.15) + (clearance 0.125) (trace_width 0.254) (via_dia 0.889) (via_drill 0.25) @@ -23115,11 +23115,6 @@ (segment (start 91.775 -65.625) (end 92.83933 -64.56067) (width 0.15) (layer F.Cu) (net 161)) (segment (start 82.925 -65.625) (end 91.775 -65.625) (width 0.15) (layer F.Cu) (net 161)) (segment (start 93.59713 -64.56067) (end 94.8102 -63.3476) (width 0.15) (layer F.Cu) (net 161)) - (segment (start 10.1253 -31) (end 11.35 -32.2247) (width 0.15) (layer F.Cu) (net 1)) - (segment (start 11.35 -32.2247) (end 11.35 -32.8253) (width 0.15) (layer F.Cu) (net 1)) - (segment (start 9.3497 -31) (end 10.1253 -31) (width 0.15) (layer F.Cu) (net 1)) - (segment (start 9.05477 -31.29493) (end 9.3497 -31) (width 0.15) (layer F.Cu) (net 1)) - (segment (start 6.75523 -31.29493) (end 9.05477 -31.29493) (width 0.15) (layer F.Cu) (net 1)) (segment (start 10.625 -32.525) (end 10.625 -33.6) (width 0.5) (layer F.Cu) (net 303)) (segment (start 68.55 -55.85) (end 68.55 -57.175) (width 1) (layer F.Cu) (net 303)) (segment (start 89.72163 -4.9) (end 93.1 -4.9) (width 0.15) (layer F.Cu) (net 182)) @@ -29762,7 +29757,7 @@ (zone (net 237) (net_name NetC117_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 47) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29776,7 +29771,7 @@ ) (zone (net 284) (net_name PWR_18V) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 65) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29802,7 +29797,7 @@ ) (zone (net 242) (net_name NetC208_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 59) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29814,7 +29809,7 @@ ) (zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 58) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29826,7 +29821,7 @@ ) (zone (net 176) (net_name FPGA_VCCINT_1V0) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 56) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29877,7 +29872,7 @@ ) (zone (net 239) (net_name NetC118_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 50) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29890,7 +29885,7 @@ ) (zone (net 302) (net_name VCC_5V0) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 60) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -29989,7 +29984,7 @@ ) (zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer F.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 53) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30040,7 +30035,7 @@ ) (zone (net 284) (net_name PWR_18V) (layer In2.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 46) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30053,7 +30048,7 @@ ) (zone (net 284) (net_name PWR_18V) (layer In5.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 45) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30080,7 +30075,7 @@ ) (zone (net 7) (net_name GND) (layer In1.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 50) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30098,7 +30093,7 @@ ) (zone (net 303) (net_name VCCO_3V3) (layer In3.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30116,7 +30111,7 @@ ) (zone (net 176) (net_name FPGA_VCCINT_1V0) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30141,7 +30136,7 @@ ) (zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30181,7 +30176,7 @@ ) (zone (net 186) (net_name FT_MGMT_VCC3V3) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30200,7 +30195,7 @@ ) (zone (net 284) (net_name PWR_18V) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30217,7 +30212,7 @@ ) (zone (net 199) (net_name FT_VCC3V3) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon @@ -30266,7 +30261,7 @@ ) (zone (net 4) (net_name 3V3_BATT) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508) (priority 100) - (connect_pads thru_hole_only (clearance 0.15)) + (connect_pads thru_hole_only (clearance 0.125)) (min_thickness 0.05) (fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5)) (polygon |