1 files changed, 7 insertions, 4 deletions
diff --git a/fix-pcb.py b/fix-pcb.py
index 939191f..4011f06 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -235,10 +235,13 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp
     change_netclass_drill_size(board, 0.635, 0.250)
 
     # Only show a single layer while working on this
-    hide_layers_except(board, ['In5.Cu'])
+    #hide_layers_except(board, ['In5.Cu'])
+    # Only show Through Via while working on this
+    #board.SetVisibleElements(0x7FFC0009)
 
-    # Only show Through Via while working on Layer 4
-    board.SetVisibleElements(0x7FFC0009)
+    # Make a better first impression =)
+    hide_layers_except(board, ['F.Cu'])
+    board.SetVisibleElements(0x7FFED33F)
 
     pcbnew.SaveBoard(out_fn, board)
     return True
@@ -246,7 +249,7 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp
 if __name__ == '__main__':
     try:
         if len(sys.argv) != 3:
-            sys.stderr.write('Syntax: fix-layer-4.py infile.kicad_pcb outfile.kicad_pcb\n')
+            sys.stderr.write('Syntax: fix-pcb.py infile.kicad_pcb outfile.kicad_pcb\n')
             sys.exit(1)
         res = main(sys.argv[1], sys.argv[2])
         if res: