1 files changed, 44 insertions, 8 deletions

diff --git a/fix-pcb.py b/fix-pcb.py
index 83f0136..52dc67f 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -46,7 +46,7 @@ def hide_layers_except(board, layers):
     board.SetVisibleLayers(visible_set)
 
 
-def layer_zone_fixes(board, layer, clearance=0.15, min_width=0.05, thermal=0.5,
+def layer_zone_fixes(board, layer, clearance=0.125, min_width=0.05, thermal=0.5,
                      gnd_clearance=0.25, gnd_min_width=0.05, gnd_thermal=0.5, gnd_priority=50):
     for i in range(board.GetAreaCount()):
         area = board.GetArea(i)
@@ -80,19 +80,36 @@ def change_via_drill_size(board, from_size, to_drill):
     Oddly enough, these have a 'width' of 1000000 but need to have the drill size set
     to not inherit the default for the net class which will be 0.25 mm.
     """
-    sizes = {}
     from_size = pcbnew.FromMM(from_size)
     for this in board.GetTracks():
         if type(this) is pcbnew.VIA:
             size = this.GetWidth()
-            sizes[size] = sizes.get(size, 0) + 1
             if size == from_size:
                 this.SetDrill(pcbnew.FromMM(to_drill))
-            #else:
-            #    help(this)
-            #    print('Not changing drill {} to {}'.format(this.GetDrill(), to_drill))
+
+def change_via_width(board, from_, to_):
+    """
+    """
+    changed = 0
+    from_ = pcbnew.FromMM(from_)
+    for this in board.GetTracks():
+        if type(this) is pcbnew.VIA:
+            size = this.GetWidth()
+            if size == from_:
+                this.SetWidth(pcbnew.FromMM(to_))
+                changed += 1
+    print("Changed {} via's from width {} to {}".format(changed, from_, to_))
+
+
+def show_via_widths(board):
+    sizes = {}
+    for this in board.GetTracks():
+        if type(this) is pcbnew.VIA:
+            size = this.GetWidth()
+            sizes[size] = sizes.get(size, 0) + 1
     print("Via 'widths': {}".format(sizes))
 
+
 def change_netclass_drill_size(board, from_, to_):
     #help(board.GetDesignSettings())
     names = board.GetAllNetClasses()
@@ -102,6 +119,14 @@ def change_netclass_drill_size(board, from_, to_):
             net.SetViaDrill(pcbnew.FromMM(to_))
 
 
+def change_netclass_clearance(board, to_):
+    names = board.GetAllNetClasses()
+    for name, net in names.iterator():
+        old = net.GetClearance()
+        print("Netclass {} has clearance {}, changing to {}".format(name, pcbnew.ToMM(old), pcbnew.FromMM(to_)))
+        net.SetClearance(pcbnew.FromMM(to_))
+
+
 #
 # One function per layer
 #
@@ -134,7 +159,7 @@ def fix_layer_In1_aka_GP1(board):
 
       $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP1
     """
-    layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.15)
+    layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.125)
 
 
 def fix_layer_In2_aka_G1(board):
@@ -164,7 +189,6 @@ def fix_layer_In3_aka_GP2(board):
 
 def fix_layer_In4_aka_GP3(board):
     """
-
     Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made
     like an inverted layer with drawn lines separating polygons. Issues were with
     line thickness in Kicad, clearance parameters preventing copper to flow in between
@@ -176,6 +200,11 @@ def fix_layer_In4_aka_GP3(board):
       $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP3
     """
     remove_tracks(board, 'In4.Cu')
+    # GND clearance should be 0.125 to minimise diff around thoughholes in the GND polygon
+    # (best seen around the SDRAM vias on the right hand side), but that also makes the
+    # line separating the polygons thinner, so I'll keep it this way. Maybe these polygons
+    # should get a manual touch-up after conversion anyways - the isolated GND polygon in
+    # the middle has a bit of an odd shape.
     layer_zone_fixes(board, 'In4.Cu', gnd_clearance=0.25)
 
 
@@ -244,7 +273,14 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp
     fix_layer_B_aka_GBL(board)
 
     change_via_drill_size(board, 1.0, 0.5)
+    # Changing these via widths minimizes diff on layer In1/GP1, but creates diff on
+    # the top layer. Altium seems to have different internal layer clearings than KiCAD.
+    #change_via_width(board, 0.5, 0.45)
+    #change_via_width(board, 1.0, 0.7)
+    #change_via_width(board, 1.5, 1.2)
+    show_via_widths(board)
     change_netclass_drill_size(board, 0.635, 0.250)
+    change_netclass_clearance(board, 0.125)
 
     # Only show a single layer while working on this
     #hide_layers_except(board, ['In5.Cu'])