diff options
| -rwxr-xr-x | convert.sh | 13 | ||||
| -rwxr-xr-x | fix-pcb.py | 96 |
2 files changed, 57 insertions, 52 deletions
@@ -18,7 +18,8 @@ kicaddir="rev03-KiCad" test -d altium2kicad || git clone -b ft-2017-09-cryptech_mods https://github.com/fredrikt/altium2kicad rm -rf ${altiumdir} -cp -rp ../../../hardware/cad/rev03/ ${altiumdir} +test -d hardware || git clone https://git.cryptech.is/hardware.git +cp -rp hardware/cad/rev03 ${altiumdir} cd ${altiumdir} @@ -42,7 +43,7 @@ cp -rp ${altiumdir}/wrlshp ${kicaddir}/wrlshp cp "Cryptech Alpha.pro.template" "${kicaddir}/Cryptech Alpha.pro" cp "Cryptech Alpha.sch.template" "${kicaddir}/Cryptech Alpha.sch" -# Fix wrl paths +# Fix wrl paths - XXX should be made relative paths wrlpath=$(readlink -f ${altiumdir}/wrlshp) sed -i -e "s!${wrlpath}!wrlshp!g" ${kicaddir}/rev02_* @@ -73,10 +74,10 @@ ls Cryptech\ Alpha.sch rev02*sch | while read file; do num=$[$num + 1] done -# Make a copy used as input file in fix-layer-4.py -cp "Cryptech Alpha.kicad_pcb" "convert.kicad_pcb" -../fix-pcb.py "convert.kicad_pcb" "Cryptech Alpha.kicad_pcb" - +# Make further modifications to the layout using KiCAD's Python bindings +cp "Cryptech Alpha.kicad_pcb" "Cryptech Alpha.kicad_pcb.a2k-out" +../fix-pcb.py "Cryptech Alpha.kicad_pcb" "Cryptech Alpha.kicad_pcb" +diff -u "Cryptech Alpha.kicad_pcb.before-fix-pcb" "Cryptech Alpha.kicad_pcb" echo "" echo "Done. The leftovers from conversion is in ${altiumdir}, and you can start KiCad like this:" @@ -73,7 +73,28 @@ def layer_zone_fixes(board, layer, clearance=0.15, min_width=0.05, thermal=0.5, area.SetThermalReliefCopperBridge(int(thermal * 1000000)) -def fix_layer_GTL(board): +#def change_via_drill_size(board, from_, to_): +# for this in board.GetTracks(): +# if type(this) is pcbnew.VIA: +# if this.GetDrill() == from_: +# this.SetDrill(pcbnew.FromMM(to_)) +# else: +# help(this) +# print('Not changing drill {} to {}'.format(this.GetDrill(), to_)) + +def change_netclass_drill_size(board, from_, to_): + help(board.GetDesignSettings()) + names = board.GetAllNetClasses() + for name, net in names.iterator(): + if net.GetViaDrill() == int(from_ * 1000000): + print("Netclass {} has drill size {}, changing to {}".format(name, net.GetViaDrill(), int(to_ * 1000000))) + net.SetViaDrill(int(to_ * 1000000)) + + +# +# One function per layer +# +def fix_layer_F_aka_GTL(board): """ There are four segments of Net1 to the far left, just below the four vias for VCCO_3V3. Altium covers this up in the GND polygon, much the same way as on the @@ -83,7 +104,7 @@ def fix_layer_GTL(board): Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-F.Cu.gbr' /path/to/CrypTech.GTL + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-F.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GTL """ for this in [x for x in board.GetTracks() if x.GetLayerName() == 'F.Cu']: pos = tuple(this.GetStart()) @@ -93,19 +114,19 @@ def fix_layer_GTL(board): layer_zone_fixes(board, 'F.Cu', gnd_clearance=0.15) -def fix_layer_GP1(board): +def fix_layer_In1_aka_GP1(board): """ Layer 1 has a GND polygon that needs a little less clearance in order to fill in between the vias of the FPGA. Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' /path/to/CrypTech.GP1 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP1 """ layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.15) -def fix_layer_G1(board): +def fix_layer_In2_aka_G1(board): """ Layer 2 has a GND fill with unusual fill properties. We could easilly change parameters on this zone to reach many more places on the board. There are even a few isolated islands @@ -114,20 +135,20 @@ def fix_layer_G1(board): Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' /path/to/CrypTech.GP1 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In2.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.G1 """ layer_zone_fixes(board, 'In2.Cu', gnd_clearance=0.5, gnd_min_width=0.7, gnd_thermal=0.71) -def fix_layer_GP2(board): +def fix_layer_In3_aka_GP2(board): """ Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In3.Cu.gbr' /path/to/CrypTech.GP2 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In3.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP2 """ layer_zone_fixes(board, 'In3.Cu') -def fix_layer_GP3(board): +def fix_layer_In4_aka_GP3(board): """ Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made @@ -138,34 +159,34 @@ def fix_layer_GP3(board): Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' /path/to/CrypTech.GP3 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP3 """ remove_tracks(board, 'In4.Cu') layer_zone_fixes(board, 'In4.Cu', gnd_clearance=0.25) -def fix_layer_G2(board): +def fix_layer_In5_aka_G2(board): """ Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In5.Cu.gbr' /path/to/CrypTech.G2 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In5.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.G2 """ layer_zone_fixes(board, 'In5.Cu', gnd_clearance=0.5, gnd_min_width=0.7, gnd_thermal=0.71) -def fix_layer_GP4(board): +def fix_layer_In6_aka_GP4(board): """ Layer 6 has a GND polygon that needs a little less clearance in order to fill in between the vias of the FPGA. Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In6.Cu.gbr' /path/to/CrypTech.GP4 + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In6.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP4 """ layer_zone_fixes(board, 'In6.Cu', gnd_clearance=0.15) -def fix_layer_GBL(board): +def fix_layer_B_aka_GBL(board): """ There is one small segment that ends up on Net 1 instead of GND (Net 7) for some reason: @@ -184,7 +205,7 @@ def fix_layer_GBL(board): Compare with - $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr' /path/to/CrypTech.GBL + $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-B.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GBL """ for this in [x for x in board.GetTracks() if x.GetLayerName() == 'B.Cu']: if tuple(this.GetStart()) == (38750000, -74875000): @@ -194,40 +215,23 @@ def fix_layer_GBL(board): layer_zone_fixes(board, 'B.Cu', gnd_clearance=0.15) -#def change_via_drill_size(board, from_, to_): -# for this in board.GetTracks(): -# if type(this) is pcbnew.VIA: -# if this.GetDrill() == from_: -# this.SetDrill(pcbnew.FromMM(to_)) -# else: -# help(this) -# print('Not changing drill {} to {}'.format(this.GetDrill(), to_)) - -def change_netclass_drill_size(board, from_, to_): - help(board.GetDesignSettings()) - names = board.GetAllNetClasses() - for name, net in names.iterator(): - if net.GetViaDrill() == int(from_ * 1000000): - print("Netclass {} has drill size {}, changing to {}".format(name, net.GetViaDrill(), int(to_ * 1000000))) - net.SetViaDrill(int(to_ * 1000000)) - - def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alpha.kicad_pcb'): board = pcbnew.LoadBoard(in_fn) - pcbnew.SaveBoard(in_fn + '.before-fix-layer-4', board) - - fix_layer_GTL(board) - fix_layer_GP1(board) - fix_layer_G1(board) - fix_layer_GP2(board) - fix_layer_GP3(board) - fix_layer_G2(board) - fix_layer_GP4(board) - fix_layer_GBL(board) - - #change_via_drill_size(board, 0.635, 0.250) + # normalize contents to be able to use diff to show changes made + pcbnew.SaveBoard(in_fn + '.before-fix-pcb', board) + + fix_layer_F_aka_GTL(board) + fix_layer_In1_aka_GP1(board) + fix_layer_In2_aka_G1(board) + fix_layer_In3_aka_GP2(board) + fix_layer_In4_aka_GP3(board) + fix_layer_In5_aka_G2(board) + fix_layer_In6_aka_GP4(board) + fix_layer_B_aka_GBL(board) + change_netclass_drill_size(board, 0.635, 0.250) + # Only show a single layer while working on this hide_layers_except(board, ['In5.Cu']) # Only show Through Via while working on Layer 4 |