diff options
author | Fredrik Thulin <fredrik@thulin.net> | 2018-05-08 16:11:45 +0200 |
---|---|---|
committer | Fredrik Thulin <fredrik@thulin.net> | 2018-05-08 16:11:45 +0200 |
commit | c97830fa39c95ee9edf2d8413d9e5f49b27bc7d7 (patch) | |
tree | 9259dad68457e273980cdfd53cec12bb9cdd044a /rev03-KiCad/rev02_15.sch | |
parent | 1960e43de6719f3067ff6b8fc1ff500ab2e57e96 (diff) |
commit all the label changes made by current fix-label.py
Diffstat (limited to 'rev03-KiCad/rev02_15.sch')
-rw-r--r-- | rev03-KiCad/rev02_15.sch | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/rev03-KiCad/rev02_15.sch b/rev03-KiCad/rev02_15.sch index e3b70e0..b5912c2 100644 --- a/rev03-KiCad/rev02_15.sch +++ b/rev03-KiCad/rev02_15.sch @@ -341,7 +341,7 @@ Text Label 6900 6500 0 48 ~ FPGA_PROM_W_N Wire Wire Line 7000 9500 6700 9500 -Text Label 6700 9500 0 48 ~ +Text GLabel 6700 9500 0 48 Input ~ 0 FPGA_GCLK Wire Wire Line 6200 9300 6100 9300 @@ -351,41 +351,41 @@ Wire Wire Line 6200 8900 5800 8900 Wire Wire Line 3660 6830 3090 6830 -Text Label 3090 6830 0 48 ~ +Text GLabel 3090 6830 0 48 Input ~ 0 FPGA_CFG_SCLK Wire Wire Line 3660 6930 3090 6930 -Text Label 3090 6930 0 48 ~ +Text GLabel 3090 6930 0 48 Input ~ 0 FPGA_CFG_MOSI Wire Wire Line 3660 6730 3090 6730 -Text Label 3090 6730 0 48 ~ +Text GLabel 3090 6730 0 48 Input ~ 0 FPGA_CFG_CS_N Wire Wire Line 5160 7030 4660 7030 -Text Label 5160 7030 0 48 ~ +Text GLabel 5160 7030 2 48 Output ~ 0 FPGA_CFG_MISO Wire Wire Line 3660 5630 2980 5630 -Text Label 2980 5630 0 48 ~ +Text GLabel 2980 5630 0 48 Input ~ 0 ARM_FPGA_CFG_CS_N Wire Wire Line 3660 5830 2980 5830 -Text Label 2980 5830 0 48 ~ +Text GLabel 2980 5830 0 48 Input ~ 0 ARM_FPGA_CFG_MOSI Wire Wire Line 5160 5930 4660 5930 -Text Label 5160 5930 0 48 ~ +Text GLabel 5160 5930 2 48 Output ~ 0 ARM_FPGA_CFG_MISO Wire Wire Line 3660 5730 2980 5730 -Text Label 2980 5730 0 48 ~ +Text GLabel 2980 5730 0 48 Input ~ 0 ARM_FPGA_CFG_SCLK Text Label 3360 5510 1 48 ~ SPI_A_TRISTATE Text Label 3060 7230 0 48 ~ SPI_B_TRISTATE -Text Label 430 6430 0 48 ~ +Text GLabel 430 6430 0 48 Input ~ 0 FPGA_CFG_CTRL_FPGA_DIS Wire Wire Line 6300 9500 6100 9500 @@ -445,7 +445,7 @@ Wire Wire Line 3660 6130 3360 6130 Wire Wire Line 430 6130 1760 6130 -Text Label 430 6130 0 48 ~ +Text GLabel 430 6130 0 48 Input ~ 0 FPGA_CFG_CTRL_ARM_ENA Connection ~ 3360 4420 $Comp |