diff options
author | Fredrik Thulin <fredrik@thulin.net> | 2018-04-19 11:15:17 +0200 |
---|---|---|
committer | Fredrik Thulin <fredrik@thulin.net> | 2018-04-19 11:15:17 +0200 |
commit | e638a77f5a401aabbbfe3fd3ea188caead58c211 (patch) | |
tree | 9c2b8fc091a8d4122f9f8e09dea4d2bcb51eb8fa /rev03-KiCad/rev02_13.sch | |
parent | 392b0e19d13b78387d3528dfba03388acd0ef5bd (diff) |
commit changes from updated altium2kicad
Diffstat (limited to 'rev03-KiCad/rev02_13.sch')
-rw-r--r-- | rev03-KiCad/rev02_13.sch | 56 |
1 files changed, 30 insertions, 26 deletions
diff --git a/rev03-KiCad/rev02_13.sch b/rev03-KiCad/rev02_13.sch index f68d79c..94f1986 100644 --- a/rev03-KiCad/rev02_13.sch +++ b/rev03-KiCad/rev02_13.sch @@ -56,12 +56,16 @@ Text Notes 1600 9380 0 60 ~ 12 R35 Text Notes 2400 9370 0 60 ~ 12 R36 +Text Notes 6650 5500 0 60 ~ 12 +2N7002 Text Notes 6450 5510 0 60 ~ 12 Q4 Text Notes 5140 9560 2 60 ~ 12 R39 Text Notes 7860 8790 0 60 ~ 12 C108 +Text Notes 7760 8990 0 60 ~ 12 +0.1~uF Text Notes 1600 4570 0 60 ~ 12 U13 Text Notes 1050 6300 0 60 ~ 12 @@ -290,23 +294,23 @@ Connection ~ 2400 4800 Connection ~ 2400 4900 Wire Wire Line 3400 5700 2000 5700 -Text Label 2900 5700 0 70 ~ +Text Label 2900 5700 0 48 ~ FPGA_M2 Wire Wire Line 1500 9000 1500 9200 Wire Wire Line 1500 9000 900 9000 -Text Label 1000 9000 0 70 ~ +Text Label 1000 9000 0 48 ~ FPGA_M2 Wire Wire Line 3400 5800 2000 5800 -Text Label 2900 5800 0 70 ~ +Text Label 2900 5800 0 48 ~ FPGA_JTAG_TCK -Text Label 8430 8500 0 70 ~ +Text Label 8430 8500 0 48 ~ FPGA_JTAG_TCK Wire Wire Line 3400 5900 2000 5900 -Text Label 2900 5900 0 70 ~ +Text Label 2900 5900 0 48 ~ FPGA_JTAG_TDI Wire Wire Line 9000 8700 8800 8700 @@ -314,19 +318,19 @@ Wire Wire Line 9300 8700 9000 8700 Wire Wire Line 8800 8700 8430 8700 -Text Label 8430 8700 0 70 ~ +Text Label 8430 8700 0 48 ~ FPGA_JTAG_TDI Wire Wire Line 3400 6000 2000 6000 -Text Label 2900 6000 0 70 ~ +Text Label 2900 6000 0 48 ~ FPGA_JTAG_TDO Wire Wire Line 9300 8800 8430 8800 -Text Label 8430 8800 0 70 ~ +Text Label 8430 8800 0 48 ~ FPGA_JTAG_TDO Wire Wire Line 3400 6100 2000 6100 -Text Label 2900 6100 0 70 ~ +Text Label 2900 6100 0 48 ~ FPGA_JTAG_TMS Wire Wire Line 9100 8600 8900 8600 @@ -334,21 +338,21 @@ Wire Wire Line 9300 8600 9100 8600 Wire Wire Line 8900 8600 8430 8600 -Text Label 8430 8600 0 70 ~ +Text Label 8430 8600 0 48 ~ FPGA_JTAG_TMS Wire Wire Line 6200 4900 6200 5100 Wire Wire Line 7600 5100 6200 5100 -Text Label 7010 5100 0 70 ~ +Text Label 7010 5100 0 48 ~ FPGA_PROGRAM_B Wire Wire Line 3940 5300 3240 5300 -Text Label 3340 5300 0 70 ~ +Text Label 3340 5300 0 48 ~ FPGA_PROGRAM_B Wire Wire Line 3400 5100 2000 5100 -Text Label 2900 5100 0 70 ~ +Text Label 2900 5100 0 48 ~ FPGA_DONE_INT Wire Wire Line 4700 9400 4700 9500 @@ -356,28 +360,28 @@ Wire Wire Line 4700 9500 3700 9500 Wire Wire Line 5000 9500 4700 9500 -Text Label 3700 9500 0 70 ~ +Text Label 3700 9500 0 48 ~ FPGA_DONE_INT Connection ~ 4700 9500 Wire Wire Line 3400 5500 2000 5500 -Text Label 2900 5500 0 70 ~ +Text Label 2900 5500 0 48 ~ FPGA_M0 Wire Wire Line 3100 9000 2500 9000 Wire Wire Line 3100 8800 3100 9000 -Text Label 2600 9000 0 70 ~ +Text Label 2600 9000 0 48 ~ FPGA_M0 Wire Wire Line 3400 5600 2000 5600 -Text Label 2900 5600 0 70 ~ +Text Label 2900 5600 0 48 ~ FPGA_M1 Wire Wire Line 2300 9000 1700 9000 Wire Wire Line 2300 9000 2300 9200 -Text Label 1750 9000 0 70 ~ +Text Label 1750 9000 0 48 ~ FPGA_M1 Wire Wire Line 5800 4900 5800 5400 @@ -385,12 +389,12 @@ Wire Wire Line 5800 5400 4800 5400 Wire Wire Line 6000 5400 5800 5400 -Text Label 4800 5400 0 70 ~ +Text Label 4800 5400 0 48 ~ FPGA_INIT_B_INT Connection ~ 5800 5400 Wire Wire Line 3940 5200 3240 5200 -Text Label 3340 5200 0 70 ~ +Text Label 3340 5200 0 48 ~ FPGA_INIT_B_INT Wire Wire Line 6600 5600 6400 5600 @@ -398,30 +402,30 @@ Wire Wire Line 6600 5600 6600 5800 Wire Wire Line 7600 5600 6600 5600 -Text Label 7130 5600 0 70 ~ +Text Label 7130 5600 0 48 ~ FPGA_INIT_B Connection ~ 6600 5600 Wire Wire Line 4700 8900 4700 9100 Wire Wire Line 5700 9500 5400 9500 -Text Label 5400 9500 0 70 ~ +Text Label 5400 9500 0 48 ~ FPGA_DONE Wire Wire Line 3940 5400 3240 5400 -Text Label 3340 5400 0 70 ~ +Text Label 3340 5400 0 48 ~ FPGA_CFG_SCLK Wire Wire Line 2840 5200 2000 5200 -Text Label 2220 5200 0 70 ~ +Text Label 2220 5200 0 48 ~ FPGA_INIT_B_INT1 Wire Wire Line 2840 5300 2000 5300 -Text Label 2220 5300 0 70 ~ +Text Label 2220 5300 0 48 ~ FPGA_PROGRAM_B1 Wire Wire Line 2840 5400 2000 5400 -Text Label 2220 5400 0 70 ~ +Text Label 2220 5400 0 48 ~ FPGA_CFG_SCLK1 Wire Wire Line 9100 8600 9100 8200 |