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authorFredrik Thulin <fredrik@thulin.net>2016-10-20 15:20:12 +0200
committerFredrik Thulin <fredrik@thulin.net>2016-10-20 15:20:12 +0200
commitc824618371135d0b50835af0d8a5225523515bb8 (patch)
tree1737f34c0838745595e36e36669a8dc232be8ec0
parentb79623489d70d34edd0571f17cfa0082d778d17f (diff)
via size and micro fixups
-rw-r--r--rev03-KiCad/Cryptech Alpha.kicad_pcb7544
1 files changed, 3772 insertions, 3772 deletions
diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb
index f9c9232..0146ef1 100644
--- a/rev03-KiCad/Cryptech Alpha.kicad_pcb
+++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb
@@ -3,7 +3,7 @@
(general
(links 1412)
(no_connects 695)
- (area -32.294113 -104.25 148.466654 54.64848)
+ (area -32.294113 -104.250001 148.466654 54.64848)
(thickness 1.6)
(drawings 7054)
(tracks 9335)
@@ -15,12 +15,12 @@
(page A4)
(layers
(0 F.Cu signal)
- (1 In1.Cu signal)
- (2 In2.Cu signal)
- (3 In3.Cu signal)
- (4 In4.Cu signal)
+ (1 In1.Cu power)
+ (2 In2.Cu mixed)
+ (3 In3.Cu power)
+ (4 In4.Cu power)
(5 In5.Cu signal)
- (6 In6.Cu signal)
+ (6 In6.Cu power)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
@@ -56,8 +56,8 @@
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
- (uvias_allowed no)
- (uvia_min_size 0.508)
+ (uvias_allowed yes)
+ (uvia_min_size 0.5)
(uvia_min_drill 0.127)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
@@ -748,25 +748,25 @@
(fp_text value "Connector; Header; 10 Position" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 18 AVR_GPIO_1))
- (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 24 AVR_GPIO_7))
- (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 23 AVR_GPIO_6))
- (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 22 AVR_GPIO_5))
- (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 21 AVR_GPIO_4))
- (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 20 AVR_GPIO_3))
- (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 19 AVR_GPIO_2))
- (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 17 AVR_GPIO_0))
- (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
)
@@ -780,9 +780,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 211 MKM_AVR_MISO))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
(at (xyz 0 0 0))
@@ -864,9 +864,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 283 PWR_18V))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -885,9 +885,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 224 NetC5_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -906,9 +906,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 301 VCC_5V0))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -927,9 +927,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 283 PWR_18V))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -1011,9 +1011,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 5 15V_STABLE))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 225 NetC11_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1032,9 +1032,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 226 NetC12_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1053,9 +1053,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 5 15V_STABLE))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -1074,9 +1074,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 275 NOISE_IN))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1095,9 +1095,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 287 RAW_NOISE))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 7 NetC15_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1116,9 +1116,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1137,9 +1137,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 227 NetC17_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1158,9 +1158,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 279 OSC_OUT))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1179,9 +1179,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1200,9 +1200,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 277 NRST))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1326,9 +1326,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -1347,9 +1347,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -1368,9 +1368,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1389,9 +1389,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1410,9 +1410,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1431,9 +1431,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1452,9 +1452,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1473,9 +1473,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1494,9 +1494,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1515,9 +1515,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1536,9 +1536,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1557,9 +1557,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1578,9 +1578,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1599,9 +1599,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1620,9 +1620,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1641,9 +1641,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
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- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1662,9 +1662,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1683,9 +1683,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1704,9 +1704,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1725,9 +1725,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1746,9 +1746,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1767,9 +1767,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1788,9 +1788,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1809,9 +1809,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1830,9 +1830,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1851,9 +1851,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1872,9 +1872,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1893,9 +1893,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1914,9 +1914,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1935,9 +1935,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1956,9 +1956,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1977,9 +1977,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -1998,9 +1998,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2019,9 +2019,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2040,9 +2040,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2061,9 +2061,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2082,9 +2082,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2103,9 +2103,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2124,9 +2124,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2145,9 +2145,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2166,9 +2166,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2187,9 +2187,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2208,9 +2208,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2229,9 +2229,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2250,9 +2250,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 228 NetC70_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2271,9 +2271,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 229 NetC71_2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2292,9 +2292,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 205 FT_VREGIN))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2313,9 +2313,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 205 FT_VREGIN))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2334,9 +2334,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 202 FT_VCCORE))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2355,9 +2355,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 230 NetC75_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2376,9 +2376,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 200 FT_VCCA))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2397,9 +2397,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 203 FT_VPHY))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2418,9 +2418,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 231 NetC78_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2439,9 +2439,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 203 FT_VPHY))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2460,9 +2460,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 204 FT_VPLL))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2481,9 +2481,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 204 FT_VPLL))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2502,9 +2502,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2523,9 +2523,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2544,9 +2544,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2565,9 +2565,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2586,9 +2586,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2607,9 +2607,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
(net 188 FT_MGMT_VREGIN))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2628,9 +2628,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 188 FT_MGMT_VREGIN))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2649,9 +2649,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 201 FT_VCCORE1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2670,9 +2670,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 232 NetC90_2))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2691,9 +2691,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 199 FT_VCCA1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2712,9 +2712,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 186 FT_MGMT_VPHY))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2733,9 +2733,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 233 NetC93_2))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2754,9 +2754,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 186 FT_MGMT_VPHY))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2775,9 +2775,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 187 FT_MGMT_VPLL))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2796,9 +2796,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 187 FT_MGMT_VPLL))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2817,9 +2817,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2838,9 +2838,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2859,9 +2859,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2880,9 +2880,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2901,9 +2901,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2922,9 +2922,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -2943,9 +2943,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2964,9 +2964,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -2985,9 +2985,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3006,9 +3006,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3027,9 +3027,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3048,9 +3048,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3069,9 +3069,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3090,9 +3090,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3111,9 +3111,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3132,9 +3132,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3195,9 +3195,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 234 NetC115_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3216,9 +3216,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 235 NetC116_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3237,9 +3237,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 236 NetC117_1))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 237 NetC117_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3258,9 +3258,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 239 NetC118_2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 238 NetC118_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3321,9 +3321,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3342,9 +3342,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3384,9 +3384,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3405,9 +3405,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3468,9 +3468,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3489,9 +3489,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3510,9 +3510,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3531,9 +3531,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3552,9 +3552,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3594,9 +3594,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3615,9 +3615,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3636,9 +3636,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3678,9 +3678,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3699,9 +3699,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3720,9 +3720,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3741,9 +3741,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3762,9 +3762,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3783,9 +3783,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3804,9 +3804,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3825,9 +3825,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3846,9 +3846,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3867,9 +3867,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3888,9 +3888,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3909,9 +3909,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3930,9 +3930,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3951,9 +3951,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -3972,9 +3972,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -3993,9 +3993,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4014,9 +4014,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4035,9 +4035,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4056,9 +4056,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4077,9 +4077,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4098,9 +4098,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4119,9 +4119,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4140,9 +4140,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4161,9 +4161,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4182,9 +4182,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4203,9 +4203,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4224,9 +4224,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 175 FPGA_VCCINT_1V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4329,9 +4329,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4350,9 +4350,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4371,9 +4371,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4392,9 +4392,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4413,9 +4413,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4434,9 +4434,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4455,9 +4455,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4476,9 +4476,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4497,9 +4497,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4518,9 +4518,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4539,9 +4539,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4560,9 +4560,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
(at (xyz 0 0 0))
@@ -4581,9 +4581,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4602,9 +4602,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4623,9 +4623,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4644,9 +4644,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4665,9 +4665,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4686,9 +4686,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4707,9 +4707,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4728,9 +4728,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4749,9 +4749,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4770,9 +4770,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4791,9 +4791,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4812,9 +4812,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4833,9 +4833,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4854,9 +4854,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4875,9 +4875,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4896,9 +4896,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4917,9 +4917,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4938,9 +4938,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4959,9 +4959,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -4980,9 +4980,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5001,9 +5001,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5022,9 +5022,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5043,9 +5043,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5064,9 +5064,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5127,9 +5127,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 240 NetC207_1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5148,9 +5148,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 242 NetC208_2))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 241 NetC208_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5211,9 +5211,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 285 PWR_ENA_VCCINT))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5232,9 +5232,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 286 PWR_ENA_VCCO))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5253,9 +5253,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 284 PWR_ENA_VCCAUX))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5274,9 +5274,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 205 FT_VREGIN))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5295,9 +5295,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 188 FT_MGMT_VREGIN))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
(at (xyz 0 0 0))
@@ -5324,14 +5324,14 @@
(net 6 GND))
(pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask))
- (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask))
+ (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 41 D1_P))
- (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 40 D1_N))
- (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 205 FT_VREGIN))
(pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
@@ -5356,14 +5356,14 @@
(pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
(pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 188 FT_MGMT_VREGIN))
- (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 2 DM_N))
- (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 1 DM_P))
- (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask))
- (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+ (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask))
+ (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
@@ -5476,9 +5476,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
- (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 203 FT_VPHY))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
(at (xyz 0 0 0))
@@ -5497,9 +5497,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 204 FT_VPLL))
- (pad 1 smd rect (at -0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
(at (xyz 0 0 0))
@@ -5518,9 +5518,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
- (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 186 FT_MGMT_VPHY))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
(at (xyz 0 0 0))
@@ -5539,9 +5539,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 187 FT_MGMT_VPLL))
- (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
(at (xyz 0 0 0))
@@ -5831,16 +5831,16 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask))
- (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask))
+ (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 277 NRST))
- (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 294 SWDIO))
- (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 293 SWDCLK))
- (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/670BFB14-85C2.wrl
(at (xyz 0 0 0))
@@ -5859,17 +5859,17 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 205 FT_VREGIN))
- (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 298 USB_P))
- (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 297 USB_N))
- (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 194 FT_RXD1))
- (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 196 FT_TXD1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
(at (xyz 0 0 0))
@@ -5888,17 +5888,17 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 183 FT_MGMT_TXD1))
- (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 181 FT_MGMT_RXD1))
- (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 295 USB_MGMT_N))
- (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 296 USB_MGMT_P))
- (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 188 FT_MGMT_VREGIN))
- (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
(at (xyz 0 0 0))
@@ -5940,9 +5940,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 244 NetJP2_2))
- (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 4 15V_LDO_ENABLE))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
(at (xyz 0 0 0))
@@ -5961,17 +5961,17 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 211 MKM_AVR_MISO))
- (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 3 3V3_BATT))
- (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 213 MKM_AVR_SCK))
- (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 212 MKM_AVR_MOSI))
- (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 38 AVR_RESET))
- (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
(at (xyz 0 0 0))
@@ -5990,11 +5990,11 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 3 3V3_BATT))
- (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/836C6F64-A2E5.wrl
(at (xyz 0 0 0))
@@ -6013,17 +6013,17 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 121 FPGA_CFG_CTRL_ARM_ENA))
- (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 291 SPI_A_TRISTATE))
- (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 122 FPGA_CFG_CTRL_FPGA_DIS))
- (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 292 SPI_B_TRISTATE))
- (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 173 FPGA_PROM_W_N))
- (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
(at (xyz 0 0 0))
@@ -6042,9 +6042,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 245 NetLED1_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6063,9 +6063,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 246 NetLED2_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6084,9 +6084,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 247 NetLED3_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6105,9 +6105,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 248 NetLED4_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6126,9 +6126,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 249 NetLED9_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6147,9 +6147,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 250 NetLED10_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6168,9 +6168,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 251 NetLED11_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6189,9 +6189,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 252 NetLED12_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6210,9 +6210,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 253 NetLED13_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 129 FPGA_DONE_INT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6231,9 +6231,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 254 NetLED14_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6252,9 +6252,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 255 NetLED15_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6273,9 +6273,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 256 NetLED16_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6294,9 +6294,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 257 NetLED17_1))
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6315,9 +6315,9 @@
(fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 259 NetLED18_2))
- (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
(net 258 NetLED18_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
(at (xyz 0 0 0))
@@ -6467,9 +6467,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 283 PWR_18V))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 263 NetR1_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6488,9 +6488,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 263 NetR1_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6509,9 +6509,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 264 NetR3_2))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 263 NetR1_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6530,9 +6530,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 132 FPGA_GCLK))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 262 NetQ5_3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6551,9 +6551,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 260 NetQ1_1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 131 FPGA_ENTROPY_DISABLE))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6572,9 +6572,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 260 NetQ1_1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6593,9 +6593,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 4 15V_LDO_ENABLE))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 283 PWR_18V))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6614,9 +6614,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 265 NetR8_1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 301 VCC_5V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6635,9 +6635,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 265 NetR8_1))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6656,9 +6656,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 287 RAW_NOISE))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 275 NOISE_IN))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6677,9 +6677,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 287 RAW_NOISE))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 5 15V_STABLE))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6698,9 +6698,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 7 NetC15_2))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 8 AMPLIFIED))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6719,9 +6719,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 8 AMPLIFIED))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6740,9 +6740,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 278 OSC_IN))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 227 NetC17_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6761,9 +6761,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 39 BOOT0))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6782,9 +6782,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 248 NetLED4_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 15 ARM_LED3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6803,9 +6803,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 243 NetIC1_3))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6824,9 +6824,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 206 KSM_PROM_CS_N))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6845,9 +6845,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 290 RTC_SDA))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6866,9 +6866,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 289 RTC_SCL))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6887,9 +6887,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 288 RTC_MFP))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6908,9 +6908,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 190 FT_REF))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6929,9 +6929,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 198 FT_VCC3V3))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 192 FT_RESET))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6950,9 +6950,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 189 FT_REF1))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6971,9 +6971,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 185 FT_MGMT_VCC3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 191 FT_RESET1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -6992,9 +6992,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 38 AVR_RESET))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7013,9 +7013,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 35 AVR_LED3))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 252 NetLED12_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7034,9 +7034,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 266 NetR32_2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7055,9 +7055,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 267 NetR33_2))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7076,9 +7076,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 216 MKM_CS_N))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7097,9 +7097,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 253 NetLED13_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7118,9 +7118,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 130 FPGA_DONE))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 129 FPGA_DONE_INT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7139,9 +7139,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 154 FPGA_INIT_B_INT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7160,9 +7160,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 168 FPGA_PROGRAM_B))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7181,9 +7181,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 155 FPGA_INIT_B))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7202,9 +7202,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 161 FPGA_JTAG_TDI))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7223,9 +7223,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 163 FPGA_JTAG_TMS))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7244,9 +7244,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 160 FPGA_JTAG_TCK))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7265,9 +7265,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 291 SPI_A_TRISTATE))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7286,9 +7286,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 292 SPI_B_TRISTATE))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7307,9 +7307,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 261 NetQ5_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7328,9 +7328,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 173 FPGA_PROM_W_N))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7349,9 +7349,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 169 FPGA_PROM_CS_N))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7370,9 +7370,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 268 NetR52_1))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 301 VCC_5V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7391,9 +7391,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 269 NetR53_2))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7412,9 +7412,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 270 NetR54_1))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 301 VCC_5V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7433,9 +7433,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 271 NetR55_2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7454,9 +7454,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 237 NetC117_2))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 236 NetC117_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7475,9 +7475,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 237 NetC117_2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7496,9 +7496,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 239 NetC118_2))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 238 NetC118_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7517,9 +7517,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 239 NetC118_2))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7538,9 +7538,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 236 NetC117_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7559,9 +7559,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 238 NetC118_1))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7580,9 +7580,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 154 FPGA_INIT_B_INT))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 153 FPGA_INIT_B_INT1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7601,9 +7601,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 167 FPGA_PROGRAM_B1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 168 FPGA_PROGRAM_B))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7622,9 +7622,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 255 NetLED15_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 150 FPGA_GPIO_LED_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7643,9 +7643,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 272 NetR65_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7664,9 +7664,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 273 NetR66_1))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 301 VCC_5V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7685,9 +7685,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 241 NetC208_1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 274 NetR67_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7706,9 +7706,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 242 NetC208_2))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 241 NetC208_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7727,9 +7727,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 242 NetC208_2))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7748,9 +7748,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 241 NetC208_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7769,9 +7769,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 127 FPGA_CFG_SCLK1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 128 FPGA_CFG_SCLK))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7790,9 +7790,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 301 VCC_5V0))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 285 PWR_ENA_VCCINT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7811,9 +7811,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 301 VCC_5V0))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 280 POK_VCCAUX))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7832,9 +7832,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 280 POK_VCCAUX))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 286 PWR_ENA_VCCO))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7853,9 +7853,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 301 VCC_5V0))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 281 POK_VCCINT))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7874,9 +7874,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 281 POK_VCCINT))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 284 PWR_ENA_VCCAUX))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7895,9 +7895,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 301 VCC_5V0))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 282 POK_VCCO))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7916,9 +7916,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 258 NetLED18_1))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 301 VCC_5V0))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7937,9 +7937,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 214 MKM_CONTROL_AVR_ENA))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7958,9 +7958,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 215 MKM_CONTROL_FPGA_DIS))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -7979,9 +7979,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 37 AVR_PANIC))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8000,9 +8000,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 126 FPGA_CFG_MOSI))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 125 FPGA_CFG_MOSI1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8021,9 +8021,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 123 FPGA_CFG_MISO1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 124 FPGA_CFG_MISO))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8042,9 +8042,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 120 FPGA_CFG_CS_N))
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 119 FPGA_CFG_CS_N1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8063,9 +8063,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 196 FT_TXD1))
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 197 FT_TXD))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8084,9 +8084,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 195 FT_RXD))
- (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 194 FT_RXD1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8105,9 +8105,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 183 FT_MGMT_TXD1))
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 184 FT_MGMT_TXD))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8126,9 +8126,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 182 FT_MGMT_RXD))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 181 FT_MGMT_RXD1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8147,9 +8147,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 184 FT_MGMT_TXD))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8168,9 +8168,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 197 FT_TXD))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8189,9 +8189,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 14 ARM_LED2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 245 NetLED1_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8210,9 +8210,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 247 NetLED3_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 13 ARM_LED1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8231,9 +8231,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 16 ARM_LED4))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 246 NetLED2_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8252,9 +8252,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 249 NetLED9_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 34 AVR_LED2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8273,9 +8273,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 33 AVR_LED1))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 251 NetLED11_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8294,9 +8294,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 250 NetLED10_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 36 AVR_LED4))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8315,9 +8315,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 151 FPGA_GPIO_LED_2))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 256 NetLED16_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8336,9 +8336,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 254 NetLED14_1))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 152 FPGA_GPIO_LED_3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8357,9 +8357,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 149 FPGA_GPIO_LED_0))
- (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
(net 257 NetLED17_1))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -8422,9 +8422,9 @@
(fp_text value TACTILE_SWITCH (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask)
+ (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask)
+ (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
@@ -8445,21 +8445,21 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 160 FPGA_JTAG_TCK))
- (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 163 FPGA_JTAG_TMS))
- (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 161 FPGA_JTAG_TDI))
- (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 162 FPGA_JTAG_TDO))
- (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A962434E-CFE5.wrl
(at (xyz 0 0 0))
@@ -8478,37 +8478,37 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 140 FPGA_GPIO_A_7))
- (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 139 FPGA_GPIO_A_6))
- (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 138 FPGA_GPIO_A_5))
- (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 137 FPGA_GPIO_A_4))
- (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 136 FPGA_GPIO_A_3))
- (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 135 FPGA_GPIO_A_2))
- (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 134 FPGA_GPIO_A_1))
- (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 133 FPGA_GPIO_A_0))
- (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
(at (xyz 0 0 0))
@@ -8527,37 +8527,37 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 302 VCCO_3V3))
- (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 141 FPGA_GPIO_B_0))
- (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 142 FPGA_GPIO_B_1))
- (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 143 FPGA_GPIO_B_2))
- (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 144 FPGA_GPIO_B_3))
- (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 6 GND))
- (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 145 FPGA_GPIO_B_4))
- (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 146 FPGA_GPIO_B_5))
- (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 147 FPGA_GPIO_B_6))
- (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+ (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
(net 148 FPGA_GPIO_B_7))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
(at (xyz 0 0 0))
@@ -9488,21 +9488,21 @@
(fp_text value SOIC127P600X175-8N (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 8 smd rect (at 2.6924 -1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 8 smd rect (at 2.6924 -1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
- (pad 7 smd rect (at 2.6924 -0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 7 smd rect (at 2.6924 -0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 288 RTC_MFP))
- (pad 6 smd rect (at 2.6924 0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 6 smd rect (at 2.6924 0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 289 RTC_SCL))
- (pad 5 smd rect (at 2.6924 1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 5 smd rect (at 2.6924 1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 290 RTC_SDA))
- (pad 4 smd rect (at -2.7178 1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 4 smd rect (at -2.7178 1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 3 smd rect (at -2.7178 0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 3 smd rect (at -2.7178 0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 3V3_BATT))
- (pad 2 smd rect (at -2.7178 -0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -2.7178 -0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 229 NetC71_2))
- (pad 1 smd rect (at -2.7178 -1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -2.7178 -1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
(net 228 NetC70_2))
)
@@ -9791,20 +9791,20 @@
(fp_text value SOIC127P600X175-8N (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 216 MKM_CS_N))
- (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 221 MKM_MISO))
- (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask))
- (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask))
+ (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad 5 smd rect (at 1.905 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 5 smd rect (at 1.905 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 222 MKM_MOSI))
- (pad 6 smd rect (at 0.635 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 6 smd rect (at 0.635 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 223 MKM_SCK))
- (pad 7 smd rect (at -0.635 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 7 smd rect (at -0.635 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 267 NetR33_2))
- (pad 8 smd rect (at -1.905 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+ (pad 8 smd rect (at -1.905 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
(net 3 3V3_BATT))
)
@@ -9818,758 +9818,758 @@
(fp_text value "BGA, 484-Leads, Body 23,00x23,00mmx2,54mm, Pitch 1,00mm" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad AB22 smd circle (at -10.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 63 FMC_A20))
- (pad AB21 smd circle (at -9.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 62 FMC_A19))
- (pad AB20 smd circle (at -8.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 64 FMC_A21))
- (pad AB19 smd circle (at -7.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad AB18 smd circle (at -6.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 67 FMC_A24))
- (pad AB17 smd circle (at -5.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 47 FMC_A4))
- (pad AB16 smd circle (at -4.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 44 FMC_A1))
- (pad AB15 smd circle (at -3.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 51 FMC_A8))
- (pad AB14 smd circle (at -2.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad AB13 smd circle (at -1.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 49 FMC_A6))
- (pad AB12 smd circle (at -0.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 57 FMC_A14))
- (pad AB11 smd circle (at 0.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 74 FMC_D4))
- (pad AB10 smd circle (at 1.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 55 FMC_A12))
- (pad AB9 smd circle (at 2.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad AB8 smd circle (at 3.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 58 FMC_A15))
- (pad AB7 smd circle (at 4.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 70 FMC_D0))
- (pad AB6 smd circle (at 5.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 71 FMC_D1))
- (pad AB5 smd circle (at 6.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 90 FMC_D20))
- (pad AB4 smd circle (at 7.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad AB3 smd circle (at 8.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 86 FMC_D16))
- (pad AB2 smd circle (at 9.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 85 FMC_D15))
- (pad AB1 smd circle (at 10.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 84 FMC_D14))
- (pad AA22 smd circle (at -10.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad AA21 smd circle (at -9.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 79 FMC_D9))
- (pad AA20 smd circle (at -8.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 152 FPGA_GPIO_LED_3))
- (pad AA19 smd circle (at -7.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 68 FMC_A25))
- (pad AA18 smd circle (at -6.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad AA17 smd circle (at -5.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad AA16 smd circle (at -4.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 45 FMC_A2))
- (pad AA15 smd circle (at -3.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 50 FMC_A7))
- (pad AA14 smd circle (at -2.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 53 FMC_A10))
- (pad AA13 smd circle (at -1.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 48 FMC_A5))
- (pad AA12 smd circle (at -0.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad AA11 smd circle (at 0.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 75 FMC_D5))
- (pad AA10 smd circle (at 1.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad AA9 smd circle (at 2.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 59 FMC_A16))
- (pad AA8 smd circle (at 3.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 60 FMC_A17))
- (pad AA7 smd circle (at 4.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad AA6 smd circle (at 5.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 110 FMC_NWE))
- (pad AA5 smd circle (at 6.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 89 FMC_D19))
- (pad AA4 smd circle (at 7.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 92 FMC_D22))
- (pad AA3 smd circle (at 8.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 88 FMC_D18))
- (pad AA2 smd circle (at 9.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad AA1 smd circle (at 10.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 83 FMC_D13))
- (pad Y22 smd circle (at -10.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 66 FMC_A23))
- (pad Y21 smd circle (at -9.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 65 FMC_A22))
- (pad Y20 smd circle (at -8.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad Y19 smd circle (at -7.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad Y18 smd circle (at -6.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 78 FMC_D8))
- (pad Y17 smd circle (at -5.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 43 FMC_A0))
- (pad Y16 smd circle (at -4.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 46 FMC_A3))
- (pad Y15 smd circle (at -3.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad Y14 smd circle (at -2.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 54 FMC_A11))
- (pad Y13 smd circle (at -1.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 52 FMC_A9))
- (pad Y12 smd circle (at -0.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 77 FMC_D7))
- (pad Y11 smd circle (at 0.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 76 FMC_D6))
- (pad Y10 smd circle (at 1.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad Y9 smd circle (at 2.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad Y8 smd circle (at 3.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad Y7 smd circle (at 4.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 61 FMC_A18))
- (pad Y6 smd circle (at 5.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 109 FMC_NWAIT))
- (pad Y5 smd circle (at 6.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad Y4 smd circle (at 7.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 91 FMC_D21))
- (pad Y3 smd circle (at 8.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 87 FMC_D17))
- (pad Y2 smd circle (at 9.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad Y1 smd circle (at 10.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 218 MKM_FPGA_MISO))
- (pad W22 smd circle (at -10.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 151 FPGA_GPIO_LED_2))
- (pad W21 smd circle (at -9.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W20 smd circle (at -8.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 80 FMC_D10))
- (pad W19 smd circle (at -7.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 42 DIGITIZED_NOISE))
- (pad W18 smd circle (at -6.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad W17 smd circle (at -5.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 107 FMC_NL))
- (pad W16 smd circle (at -4.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 108 FMC_NOE))
- (pad W15 smd circle (at -3.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W14 smd circle (at -2.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 97 FMC_D27))
- (pad W13 smd circle (at -1.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad W12 smd circle (at -0.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 96 FMC_D26))
- (pad W11 smd circle (at 0.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 69 FMC_CLK))
- (pad W10 smd circle (at 1.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 94 FMC_D24))
- (pad W9 smd circle (at 2.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W8 smd circle (at 3.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad W7 smd circle (at 4.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W6 smd circle (at 5.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W5 smd circle (at 6.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W4 smd circle (at 7.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad W3 smd circle (at 8.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad W2 smd circle (at 9.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 217 MKM_FPGA_CS_N))
- (pad W1 smd circle (at 10.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 219 MKM_FPGA_MOSI))
- (pad V22 smd circle (at -10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V21 smd circle (at -9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad V20 smd circle (at -8.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 98 FMC_D28))
- (pad V19 smd circle (at -7.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V18 smd circle (at -6.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 99 FMC_D29))
- (pad V17 smd circle (at -5.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V16 smd circle (at -4.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad V15 smd circle (at -3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V14 smd circle (at -2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V13 smd circle (at -1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V12 smd circle (at -0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 160 FPGA_JTAG_TCK))
- (pad V11 smd circle (at 0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad V10 smd circle (at 1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V9 smd circle (at 2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V8 smd circle (at 3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V7 smd circle (at 4.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad V6 smd circle (at 5.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad V5 smd circle (at 6.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 106 FMC_NE1))
- (pad V4 smd circle (at 7.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 93 FMC_D23))
- (pad V3 smd circle (at 8.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 220 MKM_FPGA_SCK))
- (pad V2 smd circle (at 9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 56 FMC_A13))
- (pad V1 smd circle (at 10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad U22 smd circle (at -10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 272 NetR65_1))
- (pad U21 smd circle (at -9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U20 smd circle (at -8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 82 FMC_D12))
- (pad U19 smd circle (at -7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad U18 smd circle (at -6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U17 smd circle (at -5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U16 smd circle (at -4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U15 smd circle (at -3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U14 smd circle (at -2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad U13 smd circle (at -1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 162 FPGA_JTAG_TDO))
- (pad U12 smd circle (at -0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 153 FPGA_INIT_B_INT1))
- (pad U11 smd circle (at 0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 164 FPGA_M0))
- (pad U10 smd circle (at 1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 165 FPGA_M1))
- (pad U9 smd circle (at 2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 166 FPGA_M2))
- (pad U8 smd circle (at 3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad U7 smd circle (at 4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U6 smd circle (at 5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U5 smd circle (at 6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad U4 smd circle (at 7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad U3 smd circle (at 8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 149 FPGA_GPIO_LED_0))
- (pad U2 smd circle (at 9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 73 FMC_D3))
- (pad U1 smd circle (at 10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 72 FMC_D2))
- (pad T22 smd circle (at -10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad T21 smd circle (at -9.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T20 smd circle (at -8.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T19 smd circle (at -7.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 119 FPGA_CFG_CS_N1))
- (pad T18 smd circle (at -6.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T17 smd circle (at -5.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad T16 smd circle (at -4.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T15 smd circle (at -3.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T14 smd circle (at -2.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T13 smd circle (at -1.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 163 FPGA_JTAG_TMS))
- (pad T12 smd circle (at -0.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad T11 smd circle (at 0.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad T10 smd circle (at 1.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad T9 smd circle (at 2.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad T8 smd circle (at 3.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad T7 smd circle (at 4.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad T6 smd circle (at 5.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T5 smd circle (at 6.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T4 smd circle (at 7.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T3 smd circle (at 8.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad T2 smd circle (at 9.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad T1 smd circle (at 10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 150 FPGA_GPIO_LED_1))
- (pad R22 smd circle (at -10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 123 FPGA_CFG_MISO1))
- (pad R21 smd circle (at -9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 100 FMC_D30))
- (pad R20 smd circle (at -8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad R19 smd circle (at -7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R18 smd circle (at -6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R17 smd circle (at -5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R16 smd circle (at -4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R15 smd circle (at -3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad R14 smd circle (at -2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R13 smd circle (at -1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 161 FPGA_JTAG_TDI))
- (pad R12 smd circle (at -0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad R11 smd circle (at 0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad R10 smd circle (at 1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad R9 smd circle (at 2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad R8 smd circle (at 3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad R7 smd circle (at 4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad R6 smd circle (at 5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R5 smd circle (at 6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad R4 smd circle (at 7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 95 FMC_D25))
- (pad R3 smd circle (at 8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R2 smd circle (at 9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad R1 smd circle (at 10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P22 smd circle (at -10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 125 FPGA_CFG_MOSI1))
- (pad P21 smd circle (at -9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 101 FMC_D31))
- (pad P20 smd circle (at -8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P19 smd circle (at -7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P18 smd circle (at -6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad P17 smd circle (at -5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P16 smd circle (at -4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P15 smd circle (at -3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P14 smd circle (at -2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P13 smd circle (at -1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad P12 smd circle (at -0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad P11 smd circle (at 0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad P10 smd circle (at 1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad P9 smd circle (at 2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad P8 smd circle (at 3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad P7 smd circle (at 4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad P6 smd circle (at 5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P5 smd circle (at 6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P4 smd circle (at 7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P3 smd circle (at 8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad P2 smd circle (at 9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad P1 smd circle (at 10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N22 smd circle (at -10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N21 smd circle (at -9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad N20 smd circle (at -8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N19 smd circle (at -7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N18 smd circle (at -6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N17 smd circle (at -5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N16 smd circle (at -4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad N15 smd circle (at -3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 81 FMC_D11))
- (pad N14 smd circle (at -2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N13 smd circle (at -1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N12 smd circle (at -0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 167 FPGA_PROGRAM_B1))
- (pad N11 smd circle (at 0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad N10 smd circle (at 1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad N9 smd circle (at 2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad N8 smd circle (at 3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad N7 smd circle (at 4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad N6 smd circle (at 5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad N5 smd circle (at 6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N4 smd circle (at 7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N3 smd circle (at 8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N2 smd circle (at 9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad N1 smd circle (at 10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad M22 smd circle (at -10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M21 smd circle (at -9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M20 smd circle (at -8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M19 smd circle (at -7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad M18 smd circle (at -6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M17 smd circle (at -5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M16 smd circle (at -4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M15 smd circle (at -3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M14 smd circle (at -2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad M13 smd circle (at -1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M12 smd circle (at -0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad M11 smd circle (at 0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad M10 smd circle (at 1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad M9 smd circle (at 2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M8 smd circle (at 3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad M7 smd circle (at 4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad M6 smd circle (at 5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M5 smd circle (at 6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M4 smd circle (at 7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad M3 smd circle (at 8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M2 smd circle (at 9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad M1 smd circle (at 10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L22 smd circle (at -10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad L21 smd circle (at -9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L20 smd circle (at -8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L19 smd circle (at -7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L18 smd circle (at -6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L17 smd circle (at -5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad L16 smd circle (at -4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L15 smd circle (at -3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L14 smd circle (at -2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L13 smd circle (at -1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L12 smd circle (at -0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 127 FPGA_CFG_SCLK1))
- (pad L11 smd circle (at 0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L11 smd circle (at 0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad L10 smd circle (at 1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L9 smd circle (at 2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L10 smd circle (at 1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L9 smd circle (at 2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad L8 smd circle (at 3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L8 smd circle (at 3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad L7 smd circle (at 4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L7 smd circle (at 4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad L6 smd circle (at 5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L5 smd circle (at 6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L4 smd circle (at 7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L3 smd circle (at 8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad L2 smd circle (at 9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad L1 smd circle (at 10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K22 smd circle (at -10.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K21 smd circle (at -9.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K20 smd circle (at -8.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad L6 smd circle (at 5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L5 smd circle (at 6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L4 smd circle (at 7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L3 smd circle (at 8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad L2 smd circle (at 9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad L1 smd circle (at 10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K22 smd circle (at -10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K21 smd circle (at -9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K20 smd circle (at -8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad K19 smd circle (at -7.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K18 smd circle (at -6.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K17 smd circle (at -5.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K16 smd circle (at -4.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K15 smd circle (at -3.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad K14 smd circle (at -2.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K13 smd circle (at -1.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K12 smd circle (at -0.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K19 smd circle (at -7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K18 smd circle (at -6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K17 smd circle (at -5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K16 smd circle (at -4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K15 smd circle (at -3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad K14 smd circle (at -2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K13 smd circle (at -1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K12 smd circle (at -0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad K11 smd circle (at 0.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K11 smd circle (at 0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad K10 smd circle (at 1.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K10 smd circle (at 1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad K9 smd circle (at 2.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K9 smd circle (at 2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad K8 smd circle (at 3.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K8 smd circle (at 3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad K7 smd circle (at 4.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad K6 smd circle (at 5.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K5 smd circle (at 6.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad K4 smd circle (at 7.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K3 smd circle (at 8.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K2 smd circle (at 9.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad K1 smd circle (at 10.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J22 smd circle (at -10.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J21 smd circle (at -9.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J20 smd circle (at -8.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J19 smd circle (at -7.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J18 smd circle (at -6.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad J17 smd circle (at -5.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J16 smd circle (at -4.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J15 smd circle (at -3.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J14 smd circle (at -2.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J13 smd circle (at -1.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad K7 smd circle (at 4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad K6 smd circle (at 5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K5 smd circle (at 6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad K4 smd circle (at 7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K3 smd circle (at 8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J16 smd circle (at -4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J15 smd circle (at -3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J14 smd circle (at -2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J13 smd circle (at -1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad J12 smd circle (at -0.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J12 smd circle (at -0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad J11 smd circle (at 0.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J11 smd circle (at 0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad J10 smd circle (at 1.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J10 smd circle (at 1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad J9 smd circle (at 2.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J9 smd circle (at 2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad J8 smd circle (at 3.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J8 smd circle (at 3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad J7 smd circle (at 4.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J7 smd circle (at 4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad J6 smd circle (at 5.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J5 smd circle (at 6.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J4 smd circle (at 7.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J3 smd circle (at 8.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J6 smd circle (at 5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J5 smd circle (at 6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J4 smd circle (at 7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J3 smd circle (at 8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad J2 smd circle (at 9.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad J1 smd circle (at 10.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H22 smd circle (at -10.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H21 smd circle (at -9.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad H20 smd circle (at -8.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H19 smd circle (at -7.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H18 smd circle (at -6.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H17 smd circle (at -5.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H16 smd circle (at -4.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad J2 smd circle (at 9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad J1 smd circle (at 10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H22 smd circle (at -10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H21 smd circle (at -9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad H20 smd circle (at -8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H19 smd circle (at -7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H18 smd circle (at -6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H17 smd circle (at -5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H16 smd circle (at -4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad H15 smd circle (at -3.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H14 smd circle (at -2.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H13 smd circle (at -1.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H12 smd circle (at -0.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H15 smd circle (at -3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H14 smd circle (at -2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H13 smd circle (at -1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H12 smd circle (at -0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 174 FPGA_VCCAUX_1V8))
- (pad H11 smd circle (at 0.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H11 smd circle (at 0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad H10 smd circle (at 1.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H10 smd circle (at 1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad H9 smd circle (at 2.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H9 smd circle (at 2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad H8 smd circle (at 3.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H8 smd circle (at 3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 175 FPGA_VCCINT_1V0))
- (pad H7 smd circle (at 4.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H7 smd circle (at 4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad H6 smd circle (at 5.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H6 smd circle (at 5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad H5 smd circle (at 6.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H4 smd circle (at 7.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H3 smd circle (at 8.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H2 smd circle (at 9.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad H1 smd circle (at 10.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad G22 smd circle (at -10.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G21 smd circle (at -9.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G20 smd circle (at -8.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G19 smd circle (at -7.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad H5 smd circle (at 6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H4 smd circle (at 7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H3 smd circle (at 8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H2 smd circle (at 9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad H1 smd circle (at 10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad G22 smd circle (at -10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G21 smd circle (at -9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G20 smd circle (at -8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G19 smd circle (at -7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad G18 smd circle (at -6.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G17 smd circle (at -5.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G16 smd circle (at -4.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G15 smd circle (at -3.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G14 smd circle (at -2.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G18 smd circle (at -6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G17 smd circle (at -5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G16 smd circle (at -4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G15 smd circle (at -3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G14 smd circle (at -2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G13 smd circle (at -1.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G12 smd circle (at -0.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G13 smd circle (at -1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G12 smd circle (at -0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G11 smd circle (at 0.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G11 smd circle (at 0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 129 FPGA_DONE_INT))
- (pad G10 smd circle (at 1.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G10 smd circle (at 1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G9 smd circle (at 2.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G9 smd circle (at 2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G8 smd circle (at 3.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G8 smd circle (at 3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G7 smd circle (at 4.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G7 smd circle (at 4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G6 smd circle (at 5.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G6 smd circle (at 5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G5 smd circle (at 6.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G5 smd circle (at 6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad G4 smd circle (at 7.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G3 smd circle (at 8.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G2 smd circle (at 9.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad G1 smd circle (at 10.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F22 smd circle (at -10.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad G4 smd circle (at 7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G3 smd circle (at 8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G2 smd circle (at 9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad G1 smd circle (at 10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad F21 smd circle (at -9.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F20 smd circle (at -8.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F19 smd circle (at -7.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F18 smd circle (at -6.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F17 smd circle (at -5.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F19 smd circle (at -7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F18 smd circle (at -6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F17 smd circle (at -5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad F16 smd circle (at -4.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F16 smd circle (at -4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 157 FPGA_IRQ_N_1))
- (pad F15 smd circle (at -3.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F14 smd circle (at -2.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F15 smd circle (at -3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F14 smd circle (at -2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 156 FPGA_IRQ_N_0))
- (pad F13 smd circle (at -1.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F12 smd circle (at -0.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F13 smd circle (at -1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F12 smd circle (at -0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad F11 smd circle (at 0.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad F10 smd circle (at 1.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F9 smd circle (at 2.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F8 smd circle (at 3.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F7 smd circle (at 4.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F6 smd circle (at 5.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F5 smd circle (at 6.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad F4 smd circle (at 7.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F3 smd circle (at 8.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad F2 smd circle (at 9.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F11 smd circle (at 0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad F10 smd circle (at 1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F9 smd circle (at 2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F8 smd circle (at 3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F7 smd circle (at 4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F6 smd circle (at 5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F5 smd circle (at 6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad F4 smd circle (at 7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F3 smd circle (at 8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad F2 smd circle (at 9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad F1 smd circle (at 10.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E22 smd circle (at -10.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E21 smd circle (at -9.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E20 smd circle (at -8.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad E19 smd circle (at -7.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E18 smd circle (at -6.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E17 smd circle (at -5.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad F1 smd circle (at 10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad E19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 158 FPGA_IRQ_N_2))
- (pad E16 smd circle (at -4.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E15 smd circle (at -3.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad E14 smd circle (at -2.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 133 FPGA_GPIO_A_0))
- (pad E13 smd circle (at -1.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 134 FPGA_GPIO_A_1))
- (pad E12 smd circle (at -0.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E11 smd circle (at 0.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E10 smd circle (at 1.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E9 smd circle (at 2.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E8 smd circle (at 3.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E7 smd circle (at 4.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E6 smd circle (at 5.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E5 smd circle (at 6.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E4 smd circle (at 7.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad E3 smd circle (at 8.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E2 smd circle (at 9.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad E1 smd circle (at 10.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D22 smd circle (at -10.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D21 smd circle (at -9.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D20 smd circle (at -8.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D19 smd circle (at -7.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D18 smd circle (at -6.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad E3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad E1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad D17 smd circle (at -5.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 132 FPGA_GCLK))
- (pad D16 smd circle (at -4.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D15 smd circle (at -3.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D14 smd circle (at -2.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 144 FPGA_GPIO_B_3))
- (pad D13 smd circle (at -1.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad D12 smd circle (at -0.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad D11 smd circle (at 0.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D10 smd circle (at 1.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D9 smd circle (at 2.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D8 smd circle (at 3.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad D7 smd circle (at 4.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D6 smd circle (at 5.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D5 smd circle (at 6.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D4 smd circle (at 7.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad D3 smd circle (at 8.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad D2 smd circle (at 9.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad D1 smd circle (at 10.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C22 smd circle (at -10.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 148 FPGA_GPIO_B_7))
- (pad C21 smd circle (at -9.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad C20 smd circle (at -8.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 147 FPGA_GPIO_B_6))
- (pad C19 smd circle (at -7.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C18 smd circle (at -6.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 145 FPGA_GPIO_B_4))
- (pad C17 smd circle (at -5.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C16 smd circle (at -4.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad C15 smd circle (at -3.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 142 FPGA_GPIO_B_1))
- (pad C14 smd circle (at -2.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 159 FPGA_IRQ_N_3))
- (pad C13 smd circle (at -1.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 137 FPGA_GPIO_A_4))
- (pad C12 smd circle (at -0.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad C11 smd circle (at 0.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C10 smd circle (at 1.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad C9 smd circle (at 2.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C8 smd circle (at 3.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C7 smd circle (at 4.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C6 smd circle (at 5.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad C5 smd circle (at 6.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C4 smd circle (at 7.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C3 smd circle (at 8.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad C2 smd circle (at 9.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad C1 smd circle (at 10.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad B22 smd circle (at -10.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B21 smd circle (at -9.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B20 smd circle (at -8.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 29 AVR_GPIO_FPGA_0))
- (pad B19 smd circle (at -7.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad B18 smd circle (at -6.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 131 FPGA_ENTROPY_DISABLE))
- (pad B17 smd circle (at -5.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B16 smd circle (at -4.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 143 FPGA_GPIO_B_2))
- (pad B15 smd circle (at -3.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 140 FPGA_GPIO_A_7))
- (pad B14 smd circle (at -2.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad B13 smd circle (at -1.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 138 FPGA_GPIO_A_5))
- (pad B12 smd circle (at -0.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad B11 smd circle (at 0.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B10 smd circle (at 1.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B9 smd circle (at 2.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B8 smd circle (at 3.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B7 smd circle (at 4.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B6 smd circle (at 5.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B5 smd circle (at 6.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B4 smd circle (at 7.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B3 smd circle (at 8.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad B2 smd circle (at 9.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad B1 smd circle (at 10.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
- (pad A22 smd circle (at -10.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
- (net 6 GND))
- (pad A21 smd circle (at -9.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+ (net 6 GND))
+ (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 146 FPGA_GPIO_B_5))
- (pad A20 smd circle (at -8.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 30 AVR_GPIO_FPGA_1))
- (pad A19 smd circle (at -7.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 32 AVR_GPIO_FPGA_3))
- (pad A18 smd circle (at -6.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 31 AVR_GPIO_FPGA_2))
- (pad A17 smd circle (at -5.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 302 VCCO_3V3))
- (pad A16 smd circle (at -4.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 141 FPGA_GPIO_B_0))
- (pad A15 smd circle (at -3.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 139 FPGA_GPIO_A_6))
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+ (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 136 FPGA_GPIO_A_3))
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+ (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 135 FPGA_GPIO_A_2))
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+ (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
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+ (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
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+ (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
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- (pad A7 smd circle (at 4.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
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- (pad A5 smd circle (at 6.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
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+ (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+ (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad A2 smd circle (at 9.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+ (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
(net 6 GND))
- (pad A1 smd circle (at 10.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
+ (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/041B98A5-F02D.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@@ -10922,9 +10922,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
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+ (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
- (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 166 FPGA_M2))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -10943,9 +10943,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 165 FPGA_M1))
- (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 GND))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -10964,9 +10964,9 @@
(fp_text value "" (at 0 0) (layer F.SilkS) hide
(effects (font (thickness 0.05)))
)
- (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 164 FPGA_M0))
- (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+ (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
(net 302 VCCO_3V3))
(model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
(at (xyz 0 0 0))
@@ -17165,7 +17165,7 @@
(gr_line (start 72.32 -100.2454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254))
(gr_line (start 95.32 -77.7454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254))
(gr_text "USB-\r\nUART" (at 57.25 -10.525 90) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text "Alpha rev.03\r\nRadically Open BSD License\r\nhttps://cryptech.is/" (at 16.4 -55.7 90) (layer F.SilkS)
(effects (font (size 1.599999 1.599999) (thickness 0.1)) (justify left))
@@ -17174,754 +17174,754 @@
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
)
(gr_text JP5 (at 30.8 4.2) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
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(gr_text JP6 (at 82.85 -27.25) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
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(gr_text C7 (at 72.35 -84.275) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text C11 (at 76.15 -89.9 90) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
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(gr_text C12 (at 72.4 -92.2) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
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(gr_text C13 (at 78.55 -86.675 90) (layer F.SilkS)
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(gr_text C19 (at 11.7 -21.125) (layer F.SilkS)
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(gr_text C20 (at 27.35 -23) (layer F.SilkS)
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(gr_text C35 (at 38.4 -21.6 90) (layer F.SilkS)
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(gr_text C37 (at 39.975 -21.575 90) (layer F.SilkS)
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(gr_text C47 (at 96.3 -37.7 90) (layer F.SilkS)
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(gr_text C48 (at 77.45 -42.175 90) (layer F.SilkS)
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(gr_text C49 (at 96.3 -53.95 90) (layer F.SilkS)
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(gr_text C50 (at 77.375 -57.175 90) (layer F.SilkS)
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(gr_text C55 (at 96.275 -57.025 90) (layer F.SilkS)
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(gr_text 3V3 (at 54.4 -19.57662 90) (layer F.SilkS)
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(gr_text I/O (at 58.95 -19.65162 90) (layer F.SilkS)
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(gr_text NRST (at 60.425 -19.60162 90) (layer F.SilkS)
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(gr_text N/C (at 62 -19.62662 90) (layer F.SilkS)
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(gr_text STM32_SWD (at 53.15 -24.05081) (layer F.SilkS)
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(gr_text "Avalanche Transistor" (at 76.45 -95.25) (layer F.SilkS)
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(gr_text GND (at 43.84657 -6.7468 270) (layer F.SilkS)
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(gr_text GND (at 45.52671 -6.7468 270) (layer F.SilkS)
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(gr_text MOSI (at 72.1 -41.85) (layer F.SilkS)
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(gr_text GND (at 72.425 -40.25) (layer F.SilkS)
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(gr_text SCK (at 68.35 -41.875) (layer F.SilkS)
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(gr_text MISO (at 67.95 -43.525) (layer F.SilkS)
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(gr_text AVR_ISP (at 68.4 -45.475) (layer F.SilkS)
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(gr_text "MKM Access" (at 65.7 -37.975 90) (layer F.SilkS)
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(gr_text "Backup Battery" (at 68 1.275) (layer F.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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(gr_text "18-20 VDC" (at 14.5 16.5 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
@@ -18074,7 +18074,7 @@
(effects (font (size 1.9685 1.9685) (thickness 0.1)) (justify left))
)
(gr_text "3V3 VBAT GND" (at 68.8 3.5) (layer F.SilkS)
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(gr_text "" (at 87.6808 -85.471 180) (layer B.CrtYd)
(effects (font (size 1.5748 1.5748) (thickness 0.1)) (justify left mirror))
@@ -18083,415 +18083,415 @@
(effects (font (size 1.5748 1.5748) (thickness 0.1)) (justify left mirror))
)
(gr_text C1 (at 18.45 -98.6) (layer B.SilkS)
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(gr_text C4 (at 26.8224 -85.8012) (layer B.SilkS)
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(gr_text C5 (at 26.275 -76.5) (layer B.SilkS)
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(gr_text C6 (at 26.25 -69.925) (layer B.SilkS)
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(gr_text C8 (at 12.225 -67.15) (layer B.SilkS)
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(gr_text C9 (at 15.15 -57.225) (layer B.SilkS)
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(gr_text C10 (at 15.225 -63.7) (layer B.SilkS)
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(gr_text C14 (at 91.2 -96.9) (layer B.SilkS)
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(gr_text C16 (at 78.5 -89.2) (layer B.SilkS)
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(gr_text C17 (at 27.675 -31.875) (layer B.SilkS)
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(gr_text C18 (at 29.125 -39.375) (layer B.SilkS)
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(gr_text C21 (at 48.775 -12.3) (layer B.SilkS)
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(gr_text C22 (at 56.45 -54.1) (layer B.SilkS)
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(gr_text C23 (at 56.4 -52.5) (layer B.SilkS)
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(gr_text C25 (at 70.6 -23.125 270) (layer B.SilkS)
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(gr_text C26 (at 27.45 -25.275 270) (layer B.SilkS)
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(gr_text C27 (at 47.3964 -52.959) (layer B.SilkS)
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(gr_text C28 (at 51.3588 -50.4444) (layer B.SilkS)
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(gr_text C31 (at 60.05 -15.5) (layer B.SilkS)
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(gr_text C34 (at 59.25 -48.90325 270) (layer B.SilkS)
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(gr_text C36 (at 66.175 -28.575 270) (layer B.SilkS)
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(gr_text C38 (at 46.15 -15.6) (layer B.SilkS)
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(gr_text C40 (at 30.125 -44.125 270) (layer B.SilkS)
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(gr_text C41 (at 28.65 -41.35 270) (layer B.SilkS)
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(gr_text C42 (at 70.375 -21.55) (layer B.SilkS)
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(gr_text C43 (at 40.25 -50.175) (layer B.SilkS)
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(gr_text C44 (at 44.475 -48.925) (layer B.SilkS)
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(gr_text C46 (at 30.25 -29.9 270) (layer B.SilkS)
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(gr_text C58 (at 71.05 -40.175 270) (layer B.SilkS)
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(gr_text C59 (at 71.075 -36.975 270) (layer B.SilkS)
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(gr_text C60 (at 72.275 -62.175 270) (layer B.SilkS)
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(gr_text C61 (at 89.575 -57.8 270) (layer B.SilkS)
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(gr_text C62 (at 71.025 -51.25 270) (layer B.SilkS)
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(gr_text C63 (at 89.6 -40.275 270) (layer B.SilkS)
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(gr_text C64 (at 71 -57.725 270) (layer B.SilkS)
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(gr_text C65 (at 89.55 -54 270) (layer B.SilkS)
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(gr_text C66 (at 71 -44.225 270) (layer B.SilkS)
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(gr_text C67 (at 89.525 -44.675 270) (layer B.SilkS)
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(gr_text C68 (at 71.025 -54.475 270) (layer B.SilkS)
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(gr_text C72 (at 22.72006 -3.6788) (layer B.SilkS)
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(gr_text C73 (at 13.66262 -8.1466) (layer B.SilkS)
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(gr_text C87 (at 75.96779 -15.86362 270) (layer B.SilkS)
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(gr_text C88 (at 82.03992 -14.15774 270) (layer B.SilkS)
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(gr_text C105 (at 32.2808 8.977 180) (layer B.SilkS)
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(gr_text C107 (at 74.975 -27.025 270) (layer B.SilkS)
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(gr_text C108 (at 29.6722 3.7032 270) (layer B.SilkS)
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(gr_text C111 (at 66.475 -89.175) (layer B.SilkS)
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(gr_text C113 (at 42.025 -70.925 270) (layer B.SilkS)
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(gr_text C114 (at 3.55 -43.425 270) (layer B.SilkS)
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(gr_text C115 (at 31.725 -71.25 270) (layer B.SilkS)
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(gr_text C117 (at 31.625 -82.075 270) (layer B.SilkS)
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(gr_text C118 (at 16.625 -34.65 270) (layer B.SilkS)
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(gr_text C119 (at 42.025 -77.8 270) (layer B.SilkS)
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(gr_text C120 (at 3.525 -36.95 270) (layer B.SilkS)
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(gr_text C121 (at 70.625 -93.375 270) (layer B.SilkS)
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(gr_text C205 (at 28.625 -50.25) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text C206 (at 28.525 -46.525) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text C207 (at 23.775 -65.375) (layer B.SilkS)
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)
(gr_text C208 (at 27.825 -65.4) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text C209 (at 36.625 -53.625 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text C210 (at 36.625 -60.725 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text D1 (at 80.90326 -89.79653 90) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text FB5 (at 43.5864 -86.0044) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text FB6 (at 9.2 -30.675) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text FB7 (at 41 -57.375 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text Q2 (at 89.35726 -93.99747) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text Q3 (at 25.375 -35.55) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text Q5 (at 70.675 -82.75 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R4 (at 63.85 -84.25 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R7 (at 70.45 -90.95 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R8 (at 26.275 -73.95) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R9 (at 28.875 -71.775 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R10 (at 85.4 -92.3 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R11 (at 92.02967 -85.59067) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R12 (at 84.875 -86.575) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R13 (at 79 -80.6 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R14 (at 31.425 -36.05 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R16 (at 45.15 -9 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R31 (at 27.625 -9 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R33 (at 80.175 -23.975) (layer B.SilkS)
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)
(gr_text R34 (at 74.85 -32.25 270) (layer B.SilkS)
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)
(gr_text R49 (at 69.675 -89.175) (layer B.SilkS)
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)
(gr_text R52 (at 36.025 -70.05) (layer B.SilkS)
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)
(gr_text R53 (at 30.15 -71.375 270) (layer B.SilkS)
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)
(gr_text R54 (at 11.85 -46.575) (layer B.SilkS)
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)
(gr_text R55 (at 17.725 -41.625 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R56 (at 30.2 -82.075 270) (layer B.SilkS)
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(gr_text R57 (at 28.875 -76.95 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R58 (at 18.125 -36.225 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R59 (at 16.675 -38.375 270) (layer B.SilkS)
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)
(gr_text R60 (at 37.6 -82.375) (layer B.SilkS)
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)
(gr_text R61 (at 12.975 -35.4) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R64 (at 80.45 -8.45 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R66 (at 20.925 -62.65) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R67 (at 30.9 -65.475) (layer B.SilkS)
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)
(gr_text R68 (at 28.2 -66.925) (layer B.SilkS)
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)
(gr_text R69 (at 23.775 -66.85) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R70 (at 32.45 -66.95) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R80 (at 77.075 -24) (layer B.SilkS)
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)
(gr_text R81 (at 67.525 -35.975 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R82 (at 69.3 -37.15 270) (layer B.SilkS)
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)
(gr_text R92 (at 46.625 -9 270) (layer B.SilkS)
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(gr_text R93 (at 37.575 -6.65 270) (layer B.SilkS)
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(gr_text R94 (at 39.05 -6.675 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text R95 (at 29.525 -8.95 270) (layer B.SilkS)
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)
(gr_text R96 (at 23.525 -8.94999 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R97 (at 25.525 -8.95 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R98 (at 78.85 -8.675 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R99 (at 73.35 -6.375 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text R100 (at 72.05 -6.325 270) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text S1 (at 97.2 -99) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text T1 (at 90.8592 -90.2426) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text T2 (at 85.0488 -84.72006) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text TP1 (at 88.5 -86.6) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text TP2 (at 81.8 -86.7) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U1 (at 17.02701 -86.63121) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U3 (at 78.1 -82.3) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U4 (at 64.08192 -49.68233) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U6 (at 85.55 -61.625) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U12 (at 81.875 -34.8) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U13 (at 58.2 -80.8) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U14 (at 35.325 -81) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U15 (at 14.3 -45.425) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text U16 (at 32.95 -62.65) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text "NOISY DIODE" (at 85.95 -97.075) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text "(Q2)" (at 82.95 -95.375) (layer B.SilkS)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text "" (at 31.1484 -53.51894) (layer B.SilkS)
(effects (font (size 3.22834 3.22834) (thickness 0.1)) (justify left mirror))
@@ -18503,43 +18503,43 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 56.34159 17.05551 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 54.34206 17.05551 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 52.31079 16.99201 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 50.304 17.05551 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 28.59148 16.89669 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 30.62275 16.99196 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 34.65355 16.76968 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 32.63815 17.00783 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 39.79924 16.81731 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 41.78289 16.7538 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 43.87768 16.84906 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 45.80996 16.73122 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 84.6 -30.4 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 86.6 2.2) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -18560,22 +18560,22 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 14.2158 -41.9026) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 88.52995 -72.53242) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 72.73713 -94.75655 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 31.2928 -72.4154) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 10.74222 -46.8129) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 20.255 -63.07703) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 72.56445 -29.7203) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -18584,298 +18584,298 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 72.011 -16.446) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 36.254 -13.611 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 31.1658 -75.438 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 94.23611 -38.01481 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 39.454 -19.411 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 38.054 -19.611 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 26.854 -22.411 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 12.50103 -20.25983) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 70.361 -92.246) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 74.71102 -89.03908 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 45.7962 -55.7022) (layer B.CrtYd)
(effects (font (size 0.800001 0.800001) (thickness 0.1)) (justify left))
@@ -18986,31 +18986,31 @@
(effects (font (size 0.800001 0.800001) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 76.43747 17.08717 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 74.23048 17.06796 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 73.53821 -74.14536 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 69.29848 -52.61387 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 40.55562 -85.14107) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 61.98496 -84.53263) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 74.99565 -64.04555 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 43.33297 -54.35986 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 48.3108 -82.3976 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 52.60784 -90.16957) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -19019,178 +19019,178 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 81.3054 -8.25) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 23.53945 -4.48816 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 22.35 -42.45) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 36.48774 -60.14122) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 36.202 -58.9217) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 59.654 -61.511 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 18.2636 -15.351 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 91.7194 -13.3792) (layer B.CrtYd)
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(gr_text .Designator (at 91.97629 -16.33433) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 91.97629 -14.90245) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 15.73999 -15.49578 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 16.98867 -15.45736 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 36.261 -62.796) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 36.261 -64.30667) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 36.261 -65.746) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 82.511 -4.546) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 13.21412 -41.4615 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 31.76387 -75.37179) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 33.528 -70.104) (layer B.CrtYd)
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+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 10.611 -44.446) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 10.1092 -49.911) (layer B.CrtYd)
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+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 17.94465 -62.45962 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 36.386 -68.771) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 44.93808 -60.74951 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 36.336 -67.396) (layer B.CrtYd)
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- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 13.254 -23.311 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 13.07799 -27.95057 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 13.11202 -32.13658 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 93.71681 -63.10002) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 93.65918 -65.59739) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 93.73602 -68.11398) (layer B.CrtYd)
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+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 92.21839 -71.86005) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 34.62432 -67.44122) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
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(gr_text .Designator (at 83.63125 -71.51426) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 38.361 -71.321) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 79.254 -6.486 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 36.42435 -22.26712 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 46.97446 -36.90114 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 83.51284 -23.57046) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 87.636 -9.146) (layer B.CrtYd)
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+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 7.84446 -6.755 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
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)
(gr_text .Designator (at 19.4066 -8.8994) (layer B.CrtYd)
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)
(gr_text .Designator (at 30.04707 -43.87243) (layer B.CrtYd)
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)
(gr_text .Designator (at 30.07264 -42.56839) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 30.73744 -41.3922) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 26.536 -52.646) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 26.5512 -50.139) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 40.0812 -19.7866) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 71.01869 -97.96416) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 70.861 -99.246) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 25.29075 -80.56416) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 27.754 -78.311 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 27.754 -80.511 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 87.05412 -49.97844 90) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 69.06813 -10.19361 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 51.81733 -10.27052 90) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 81.5 14.9) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -19223,7 +19223,7 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 19.775 -43.85 90) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 53.5912 -35.629 90) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -19232,7 +19232,7 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 62.1068 -91.1098) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 35.49959 -97.09523) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left))
@@ -19250,7 +19250,7 @@
(effects (font (thickness 0.1)) (justify left))
)
(gr_text .Designator (at 31.25761 9.3925 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 62.4534 -68.1348) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left mirror))
@@ -19259,160 +19259,160 @@
(effects (font (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 83.693 -81.2292 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 89.80654 -87.44144 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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)
(gr_text .Designator (at 91.34511 -92.24205) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 84.3788 -88.6714) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 27.813 -62.6364) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 25.3746 -62.6364) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 70.821 -96.811 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 13.721 -36.461 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.94867 -79.5804 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 13.7008 -40.85383 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.9278 -74.9554 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 67.0894 -88.1888) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.23734 1.89096 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 76.4286 -27.0858 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 82.2404 -17.68923 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 13.26102 -6.81202) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.64834 -55.02187 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 88.4682 -44.5984 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.61723 -44.84636 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 88.4682 -54.6568 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.5972 -57.9368 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 88.50342 -40.52467 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.5972 -52.0558 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 88.4682 -57.777 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.5932 -60.0678 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.58238 -38.05273 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 72.5682 -40.0034 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.72623 -31.2881 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 65.1764 -39.7256 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 46.5328 -49.0982) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 39.85192 -49.09626) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 66.91967 -21.74013) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.6738 -40.5892 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.69144 -44.47359 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 55.31045 -15.72135) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 48.37923 -15.63683) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 65.1764 -28.8544 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 60.6806 -48.895 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 30.2768 -40.5892 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.68781 -26.06277 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 61.94791 -15.70678) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 57.0992 -48.895 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 65.17745 -35.01391 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 51.5366 -49.0982) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 29.064 -38.296) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 29.52969 -31.7815) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 78.232 -88.2904) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 90.3732 -81.4324) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 90.8812 -95.9612) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 26.00288 -71.58339) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 25.98542 -75.443) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 26.57621 -84.4867) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 67.5386 -23.114 270) (layer B.CrtYd)
(effects (font (size 0.800001 0.800001) (thickness 0.1)) (justify left mirror))
@@ -19451,40 +19451,40 @@
(effects (font (size 0.800001 0.800001) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 34.3662 -60.2488 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 34.19147 -53.46202 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 23.81096 -45.73438) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 23.92622 -50.09522) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 6.0198 -36.4236 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 39.59631 -77.58132 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 5.9602 -43.27132 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 39.6748 -70.4596 270) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 17.4498 -66.9544) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 22.02816 -88.47785) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 21.99722 -93.39716) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 21.99722 -98.4093) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 10.25264 -38.94324 270) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left mirror))
@@ -19505,142 +19505,142 @@
(effects (font (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 68.76903 -83.43915) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 77.78326 -84.30454) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 29.1083 -34.81322) (layer B.CrtYd)
- (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 1 1) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 80.21813 -28.55773 270) (layer B.CrtYd)
(effects (font (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 74.746 -6.111 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 76.746 -6.111 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 78.746 -6.111 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 25.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 23.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 29.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 42.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 40.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 46.746 -6.611 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 70.81945 -35.95606) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 70.064 -34.896) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 77.0053 -25.56306) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
)
(gr_text .Designator (at 31.1912 -64.3128) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 25.1365 -64.29195) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 27.49942 -64.31116) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 29.78549 -62.65904) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 22.77358 -62.63982) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 80.746 -6.111 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 10.414 -35.6108) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 37.2499 -81.20623) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 14.51438 -38.878 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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)
(gr_text .Designator (at 15.21173 -36.78595 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
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(gr_text .Designator (at 31.2928 -77.216 270) (layer B.CrtYd)
- (effects (font (size 0.499999 0.499999) (thickness 0.1)) (justify left mirror))
+ (effects (font (size 0.5 0.5) (thickness 0.1)) (justify left mirror))
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+ (segment (start 75.25 -84) (end 76.25 -85) (width 0.5) (layer F.Cu) (net 6))
+ (segment (start 71.5 -84) (end 75.25 -84) (width 0.5) (layer F.Cu) (net 6))
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(segment (start 30.2 -77.3) (end 30.673 -76.827) (width 0.15) (layer F.Cu) (net 6))
@@ -21618,14 +21618,14 @@
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+ (segment (start 40.6 -66.125) (end 41.2 -66.125) (width 1) (layer F.Cu) (net 6))
+ (segment (start 42.075 -54.475) (end 42.1 -54.45) (width 1) (layer F.Cu) (net 6))
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+ (segment (start 69.70001 -53.025) (end 70.8 -53.025) (width 1) (layer F.Cu) (net 6))
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+ (via micro (at 48.5 -34.425) (size 0.5) (layers F.Cu B.Cu) (net 9))
+ (via micro (at 55.55 -40.375) (size 0.5) (layers F.Cu B.Cu) (net 9))
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(segment (start 55.55 -40.375) (end 57.9 -42.725) (width 0.164) (layer B.Cu) (net 9))
@@ -21713,10 +21713,10 @@
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- (via (at 67.25 -41.6) (size 0.499999) (layers F.Cu B.Cu) (net 10))
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+ (via micro (at 66.31364 -44.843) (size 0.5) (layers F.Cu B.Cu) (net 10))
+ (via micro (at 46 -41.875) (size 0.5) (layers F.Cu B.Cu) (net 10))
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@@ -21738,9 +21738,9 @@
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+ (via micro (at 48.00234 -31.12652) (size 0.5) (layers F.Cu B.Cu) (net 11))
+ (via micro (at 64.8 -44.35) (size 0.5) (layers F.Cu B.Cu) (net 11))
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@@ -21764,9 +21764,9 @@
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- (via (at 61.85 -37.25) (size 0.499999) (layers F.Cu B.Cu) (net 12))
+ (via micro (at 61.725 -44.875) (size 0.5) (layers F.Cu B.Cu) (net 12))
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@@ -21779,8 +21779,8 @@
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+ (via micro (at 45.975 -14.125) (size 0.5) (layers F.Cu B.Cu) (net 13))
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@@ -21789,8 +21789,8 @@
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@@ -21801,8 +21801,8 @@
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@@ -21816,8 +21816,8 @@
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@@ -21825,7 +21825,7 @@
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+ (via micro (at 53.925 -36.6) (size 0.5) (layers F.Cu B.Cu) (net 17))
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@@ -21847,7 +21847,7 @@
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@@ -21874,7 +21874,7 @@
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@@ -28876,8 +28876,8 @@
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@@ -28947,31 +28947,31 @@
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@@ -29006,15 +29006,15 @@
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@@ -29050,8 +29050,8 @@
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@@ -29082,8 +29082,8 @@
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@@ -29093,8 +29093,8 @@
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(zone (net 236) (net_name NetC117_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 47)