diff options
Diffstat (limited to 'src/rtl')
| -rw-r--r-- | src/rtl/coretest_trng.v | 111 | ||||
| -rw-r--r-- | src/rtl/novena_trng.v | 9 |
2 files changed, 64 insertions, 56 deletions
diff --git a/src/rtl/coretest_trng.v b/src/rtl/coretest_trng.v index a935f4e..17bb34c 100644 --- a/src/rtl/coretest_trng.v +++ b/src/rtl/coretest_trng.v @@ -58,7 +58,7 @@ module coretest_trng( // Internal constant and parameter definitions. //---------------------------------------------------------------- parameter I2C_ADDR_PREFIX = 4'h0; - parameter TRNG_ADDR_PREFIX = 4'h2; + parameter TRNG_ADDR_PREFIX = 4'h1; //---------------------------------------------------------------- @@ -70,8 +70,8 @@ module coretest_trng( wire coretest_we; wire [15 : 0] coretest_address; wire [31 : 0] coretest_write_data; - reg [31 : 0] coretest_read_data; - reg coretest_error; + wire [31 : 0] coretest_read_data; + wire coretest_error; // i2c connections wire i2c_rxd_syn; @@ -89,7 +89,6 @@ module coretest_trng( wire [7 : 0] i2c_debug; // trng connections. - wire trng_noise; reg trng_cs; reg trng_we; reg [7 : 0] trng_address; @@ -168,12 +167,12 @@ module coretest_trng( .avalanche_noise(noise), - .cs(trng_cs), - .we(trng_we), - .address(trng_address), - .write_data(trng_write_data), - .read_data(trng_read_data), - .error(trng_error), + .cs(coretest_cs), + .we(coretest_we), + .address(coretest_address), + .write_data(coretest_write_data), + .read_data(coretest_read_data), + .error(coretest_error), .debug(trng_debug), .debug_update(trng_debug_update), @@ -188,49 +187,55 @@ module coretest_trng( // Combinational data mux that handles addressing between // cores using the 32-bit memory like interface. //---------------------------------------------------------------- - always @* - begin : address_mux - // Default assignments. - coretest_read_data = 32'h00000000; - coretest_error = 0; - - i2c_cs = 0; - i2c_we = 0; - i2c_address = 8'h00; - i2c_write_data = 32'h00000000; - - trng_cs = 0; - trng_we = 0; - trng_address = 8'h00; - trng_write_data = 32'h00000000; - - - case (coretest_address[15 : 12]) - I2C_ADDR_PREFIX: - begin - i2c_cs = coretest_cs; - i2c_we = coretest_we; - i2c_address = coretest_address[7 : 0]; - i2c_write_data = coretest_write_data; - coretest_read_data = i2c_read_data; - coretest_error = i2c_error; - end - - TRNG_ADDR_PREFIX: - begin - trng_cs = coretest_cs; - trng_we = coretest_we; - trng_address = coretest_address[11 : 0]; - trng_write_data = coretest_write_data; - coretest_read_data = trng_read_data; - coretest_error = trng_error; - end - - default: - begin - end - endcase // case (coretest_address[15 : 8]) - end // address_mux +// always @* +// begin : address_mux +// // Default assignments. +// coretest_read_data = 32'h00000000; +// coretest_error = 0; +// +// i2c_cs = 0; +// i2c_we = 0; +// i2c_address = 8'h00; +// i2c_write_data = 32'h00000000; + +// trng_cs = 0; +// trng_we = 0; +// trng_address = 8'h00; +// trng_write_data = 32'h00000000; + +// trng_cs = coretest_cs; +// trng_we = coretest_we; +// trng_address = coretest_address[11 : 0]; +// trng_write_data = coretest_write_data; +// coretest_read_data = trng_read_data; +// coretest_error = trng_error; +// +// case (coretest_address[13 : 12]) +// I2C_ADDR_PREFIX: +// begin +// i2c_cs = coretest_cs; +// i2c_we = coretest_we; +// i2c_address = coretest_address[7 : 0]; +// i2c_write_data = coretest_write_data; +// coretest_read_data = i2c_read_data; +// coretest_error = i2c_error; +// end +// +// TRNG_ADDR_PREFIX: +// begin +// trng_cs = coretest_cs; +// trng_we = coretest_we; +// trng_address = coretest_address[11 : 0]; +// trng_write_data = coretest_write_data; +// coretest_read_data = trng_read_data; +// coretest_error = trng_error; +// end +// +// default: +// begin +// end +// endcase // case (coretest_address[15 : 12]) +// end // address_mux endmodule // coretest_trng diff --git a/src/rtl/novena_trng.v b/src/rtl/novena_trng.v index 9d722b6..3630574 100644 --- a/src/rtl/novena_trng.v +++ b/src/rtl/novena_trng.v @@ -178,13 +178,16 @@ module novena_trng( wire SDA_pd; wire SDA_int; reg clk25; + reg reset_n; initial begin - clk25 <= 1'b0; + clk25 <= 1'b0; + reset_n <= 1'b0; end always @ (posedge clk) begin clk25 <= ~clk25; + reset_n <= 1'b1; EIM_A16 <= 1'b0; EIM_A17 <= 1'b0; end @@ -200,8 +203,8 @@ module novena_trng( ); coretest_trng coretest_trng_inst( - .clk(clk25), - .reset_n(1'b1), + .clk(clk), + .reset_n(reset_n), .noise(F_DX7), .debug(test_debug), |