###  Autogenerated on 2013-May-10 01:38 by edifToUcf.py
###  Extracting designator U800 from EDIF netlist novena-dvt.EDF

### extended performance annotation
CONFIG VCCAUX  = 3.3;
# Valid values are 2.5 and 3.3
CONFIG MCB_PERFORMANCE  = EXTENDED;

NET "APOPTOSIS" LOC = K1;
NET "APOPTOSIS" IOSTANDARD = LVCMOS33;

# AUD6_TFS
# NET "DEL_CONT" LOC = A4;
# NET "DEL_CONT" IOSTANDARD = LVCMOS33;
# AUD6_TXC
# NET "DEL_RST_L" LOC = B4;
# NET "DEL_RST_L" IOSTANDARD = LVCMOS33;
# NET "AUD6_TXD" LOC = A6;
# NET "AUD6_TXD" IOSTANDARD = LVCMOS33;
# NET "AUD_MCLK" LOC = H6;
# NET "AUD_MCLK" IOSTANDARD = LVCMOS33;
# AUD_MIC_CLK
#NET "ZEROVEN" LOC = G3;
#NET "ZEROVEN" IOSTANDARD = LVCMOS33;
# NET "AUD_MIC_DAT" LOC = C5;
# NET "AUD_MIC_DAT" IOSTANDARD = LVCMOS33;

# NET "BATT_NRST" LOC = N1;
# NET "BATT_NRST" IOSTANDARD = LVCMOS33;
# NET "BATT_REFLASH_ALRT" LOC = N2;
# NET "BATT_REFLASH_ALRT" IOSTANDARD = LVCMOS33;

NET "CLK2_N" LOC = H1;
NET "CLK2_N" IOSTANDARD = LVDS_33;
NET "CLK2_N" DIFF_TERM = "TRUE";
NET "CLK2_P" LOC = H2;
NET "CLK2_P" IOSTANDARD = LVDS_33;
NET "CLK2_P" DIFF_TERM = "TRUE";

# NET "DDC_SCL" LOC = J6;
# NET "DDC_SCL" IOSTANDARD = LVCMOS33;
# NET "DDC_SDA" LOC = F2;
# NET "DDC_SDA" IOSTANDARD = LVCMOS33;

# ECSPI3_MISO
#NET "SPI1_MISO" LOC = A3;
#NET "SPI1_MISO" IOSTANDARD = LVCMOS33;
# # R13
# ECSPI3_MOSI
#NET "SPI1_MOSI" LOC = A2;
#NET "SPI1_MOSI" IOSTANDARD = LVCMOS33;
# ECSPI3_RDY
#NET "SPI1_DELI_SEL" LOC = A5;
#NET "SPI1_DELI_SEL" IOSTANDARD = LVCMOS33;
# # R15
# ECSPI3_SCLK
#NET "SPI1_SCLK" LOC = D9;
#NET "SPI1_SCLK" IOSTANDARD = LVCMOS33;
# ECSPI3_SS2
#NET "SAMPEN" LOC = B3;
#NET "SAMPEN" IOSTANDARD = LVCMOS33;

# NET "EIM_BCLK" LOC = C9;
# NET "EIM_BCLK" IOSTANDARD = LVCMOS33;
#NET "EIM_CS[0]" LOC = B11;
#NET "EIM_CS[0]" IOSTANDARD = LVCMOS33;
#NET "EIM_CS[1]" LOC = A15;
#NET "EIM_CS[1]" IOSTANDARD = LVCMOS33;

NET "EIM_DA[0]" LOC = G9;
NET "EIM_DA[0]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[0]" SLEW = SLOW;
NET "EIM_DA[1]" LOC = A10;
NET "EIM_DA[1]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[1]" SLEW = SLOW;
NET "EIM_DA[2]" LOC = F9;
NET "EIM_DA[2]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[2]" SLEW = SLOW;
NET "EIM_DA[3]" LOC = B9;
NET "EIM_DA[3]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[3]" SLEW = SLOW;
NET "EIM_DA[4]" LOC = E13;
NET "EIM_DA[4]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[4]" SLEW = SLOW;
NET "EIM_DA[5]" LOC = F13;
NET "EIM_DA[5]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[5]" SLEW = SLOW;
NET "EIM_DA[6]" LOC = A9;
NET "EIM_DA[6]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[6]" SLEW = SLOW;
NET "EIM_DA[7]" LOC = A8;
NET "EIM_DA[7]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[7]" SLEW = SLOW;
NET "EIM_DA[8]" LOC = B8;
NET "EIM_DA[8]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[8]" SLEW = SLOW;
NET "EIM_DA[9]" LOC = D8;
NET "EIM_DA[9]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[9]" SLEW = SLOW;
NET "EIM_DA[10]" LOC = D11;
NET "EIM_DA[10]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[10]" SLEW = SLOW;
NET "EIM_DA[11]" LOC = C8;
NET "EIM_DA[11]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[11]" SLEW = SLOW;
NET "EIM_DA[12]" LOC = C7;
NET "EIM_DA[12]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[12]" SLEW = SLOW;

NET "EIM_DA[13]" LOC = C11;
NET "EIM_DA[13]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[13]" SLEW = SLOW;

NET "EIM_DA[14]" LOC = C4;
NET "EIM_DA[14]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[14]" SLEW = SLOW;
NET "EIM_DA[15]" LOC = B6;
NET "EIM_DA[15]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[15]" SLEW = SLOW;

# EIM_A16
NET "EIM_A16" LOC = A11;
NET "EIM_A16" IOSTANDARD = LVCMOS33;
NET "EIM_A16" SLEW = SLOW;

# EIM_A17
NET "EIM_A17" LOC = B12;
NET "EIM_A17" IOSTANDARD = LVCMOS33;
NET "EIM_A17" SLEW = SLOW;
# EIM_A18
#NET "ENC_PBIN" LOC = D14;
#NET "ENC_PBIN" IOSTANDARD = LVCMOS33;

# EIM_LBA
#NET "EIM_LBA" LOC = B14;
#NET "EIM_LBA" IOSTANDARD = LVCMOS33;
# NET "EIM_OE" LOC = C10;
# NET "EIM_OE" IOSTANDARD = LVCMOS33;
# EIM_RW
#NET "LED3" LOC = C14;
#NET "LED3" IOSTANDARD = LVCMOS33;
# NET "EIM_WAIT" LOC = A7;
# NET "EIM_WAIT" IOSTANDARD = LVCMOS33;

# #NET "FPGA_DONE" LOC = V17;
# #NET "FPGA_DONE" IOSTANDARD = LVCMOS33;
# #NET "FPGA_HSWAPEN" LOC = D4;
# #NET "FPGA_HSWAPEN" IOSTANDARD = LVCMOS33;
# FPGA_INIT_N
#NET "LED2" LOC = U3;
#NET "LED2" IOSTANDARD = LVCMOS33;

NET "FPGA_LED2" LOC = A16;
NET "FPGA_LED2" IOSTANDARD = LVCMOS33;
NET "FPGA_LED2" SLEW = SLOW;

# NET "FPGA_LSPI_CLK" LOC = D3;
# NET "FPGA_LSPI_CLK" IOSTANDARD = LVCMOS33;
# NET "FPGA_LSPI_CS" LOC = D1;
# NET "FPGA_LSPI_CS" IOSTANDARD = LVCMOS33;
# NET "FPGA_LSPI_HOLD" LOC = E3;
# NET "FPGA_LSPI_HOLD" IOSTANDARD = LVCMOS33;
# NET "FPGA_LSPI_MISO" LOC = D2;
# NET "FPGA_LSPI_MISO" IOSTANDARD = LVCMOS33;
# NET "FPGA_LSPI_MOSI" LOC = C2;
# NET "FPGA_LSPI_MOSI" IOSTANDARD = LVCMOS33;
# NET "FPGA_LSPI_WP" LOC = C1;
# NET "FPGA_LSPI_WP" IOSTANDARD = LVCMOS33;

# #NET "FPGA_M0" LOC = T15;
# #NET "FPGA_M0" IOSTANDARD = LVCMOS33;
# #NET "FPGA_M1" LOC = N12;
# #NET "FPGA_M1" IOSTANDARD = LVCMOS33;

# #NET "FPGA_RESET_N" LOC = V2;
# #NET "FPGA_RESET_N" IOSTANDARD = TMDS_33;
# #NET "FPGA_SUSPEND" LOC = R16;
# #NET "FPGA_SUSPEND" IOSTANDARD = LVCMOS33;
# #NET "FPGA_TCK" LOC = A17;
# #NET "FPGA_TCK" IOSTANDARD = LVCMOS33;
# #NET "FPGA_TDI" LOC = D15;
# #NET "FPGA_TDI" IOSTANDARD = LVCMOS33;
# #NET "FPGA_TDO" LOC = D16;
# #NET "FPGA_TDO" IOSTANDARD = LVCMOS33;
# #NET "FPGA_TMS" LOC = B18;
# #NET "FPGA_TMS" IOSTANDARD = LVCMOS33;

# # NET "GND" LOC = A1;# A18 B7 B13 C3 C16 D5 D10 E15 G2 G5 G12 G17 H8 H10 J4 J9 J11 J15 K8 K10 L9 L11 M2 M6 M17 N13 R1 R4 R9 R14 R18 T16 U6 U12 V1 V18
# # NET "GND" IOSTANDARD = LVCMOS33;

NET "I2C3_SCL" LOC = P4;
NET "I2C3_SCL" IOSTANDARD = LVCMOS33;
NET "I2C3_SDA" LOC = P3;
NET "I2C3_SDA" IOSTANDARD = LVCMOS33;

# # NET "P1_2V" LOC = G7;# H9 H11 J8 J10 K9 K11 L8 L10 M7 M12
# # NET "P1_2V" IOSTANDARD = LVCMOS33;
# # NET "P3_3V_DELAYED" LOC = B1;# B5 B10 B15 B17 D7 D13 E2 E5 E9 E10 E14 E17 G4 G10 G15 J2 J5 J12 J14 J17 K7 M4 M9 M15 P5 P9 P10 P14 R2 R6 R12 R17 U4 U9 U14
# # NET "P3_3V_DELAYED" IOSTANDARD = LVCMOS33;

NET "RESETBMCU" LOC = F1;
NET "RESETBMCU" IOSTANDARD = LVCMOS33;

# NET "SMB_SCL" LOC = N3;
# NET "SMB_SCL" IOSTANDARD = LVCMOS33;
# NET "SMB_SDA" LOC = N4;
# NET "SMB_SDA" IOSTANDARD = LVCMOS33;

# NET "UART4_CTS" LOC = U1;
# NET "UART4_CTS" IOSTANDARD = LVCMOS33;
# NET "UART4_RTS" LOC = U2;
# NET "UART4_RTS" IOSTANDARD = LVCMOS33;
# NET "UART4_RXD" LOC = T1;
# NET "UART4_RXD" IOSTANDARD = LVCMOS33;
# NET "UART4_TXD" LOC = P1;
# NET "UART4_TXD" IOSTANDARD = LVCMOS33;

# UIM_CLK
#NET "MODES" LOC = B16;
#NET "MODES" IOSTANDARD = LVCMOS33;
# UIM_DATA
#NET "ENC_SW" LOC = A12;
#NET "ENC_SW" IOSTANDARD = LVCMOS33;
# #NET "UIM_PWR" LOC = C18;
# #NET "UIM_PWR" IOSTANDARD = SSTL15_II;
# #NET "UIM_PWRON" LOC = A14;
# #NET "UIM_PWRON" IOSTANDARD = LVCMOS33;
# UIM_RESET
#NET "SW_BACKUP" LOC = C15;
#NET "SW_BACKUP" IOSTANDARD = LVCMOS33;

##############
# DDR3
##############

# NET "F_BA[2]" IOSTANDARD = SSTL15_II;
# NET "F_BA[1]" IOSTANDARD = SSTL15_II;
# NET "F_BA[0]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[13]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[12]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[11]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[10]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[9]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[8]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[7]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[6]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[5]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[4]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[3]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[2]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[1]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_A[0]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[15]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[14]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[13]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[12]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[11]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[10]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[9]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[8]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[7]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[6]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[5]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[4]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[3]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[2]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[1]" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_D[0]" IOSTANDARD = SSTL15_II;
# NET "F_CAS_N" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_CKE" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_ODT" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_RST_N" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_RZQ" IOSTANDARD = SSTL15_II;
# NET "F_DDR3_ZIO" IOSTANDARD = SSTL15_II;
# NET "F_LDM" IOSTANDARD = SSTL15_II;
# NET "F_RAS_N" IOSTANDARD = SSTL15_II;
# NET "F_UDM" IOSTANDARD = SSTL15_II;
# NET "F_WE_N" IOSTANDARD = SSTL15_II;


# NET "F_BA[0]" LOC = H13;
# NET "F_BA[1]" LOC = H14;
# NET "F_BA[2]" LOC = K13;
# NET "F_BA[0]" OUT_TERM = UNTUNED_50;
# NET "F_BA[1]" OUT_TERM = UNTUNED_50;
# NET "F_BA[2]" OUT_TERM = UNTUNED_50;

# NET "F_CAS_N" LOC = K16;
# NET "F_CAS_N" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_A[0]" LOC = H15;
# NET "F_DDR3_A[1]" LOC = H16;
# NET "F_DDR3_A[10]" LOC = E16;
# NET "F_DDR3_A[11]" LOC = G14;
# NET "F_DDR3_A[12]" LOC = D18;
# NET "F_DDR3_A[13]" LOC = C17;
# NET "F_DDR3_A[2]" LOC = F18;
# NET "F_DDR3_A[3]" LOC = J13;
# NET "F_DDR3_A[4]" LOC = E18;
# NET "F_DDR3_A[5]" LOC = L12;
# NET "F_DDR3_A[6]" LOC = L13;
# NET "F_DDR3_A[7]" LOC = F17;
# NET "F_DDR3_A[8]" LOC = H12;
# NET "F_DDR3_A[9]" LOC = G13;
# NET "F_DDR3_A[0]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[10]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[11]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[12]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[13]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[1]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[2]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[3]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[4]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[5]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[6]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[7]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[8]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_A[9]" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_CKE" LOC = D17;
# NET "F_DDR3_CKE" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_CK_N" LOC = G18;
# NET "F_DDR3_CK_N" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_DDR3_CK_N" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_CK_P" LOC = G16;
# NET "F_DDR3_CK_P" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_DDR3_CK_P" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_D[0]" LOC = M16;
# NET "F_DDR3_D[1]" LOC = M18;
# NET "F_DDR3_D[10]" LOC = P17;
# NET "F_DDR3_D[11]" LOC = P18;
# NET "F_DDR3_D[12]" LOC = T17;
# NET "F_DDR3_D[13]" LOC = T18;
# NET "F_DDR3_D[14]" LOC = U17;
# NET "F_DDR3_D[15]" LOC = U18;
# NET "F_DDR3_D[2]" LOC = L17;
# NET "F_DDR3_D[3]" LOC = L18;
# NET "F_DDR3_D[4]" LOC = H17;
# NET "F_DDR3_D[5]" LOC = H18;
# NET "F_DDR3_D[6]" LOC = J16;
# NET "F_DDR3_D[7]" LOC = J18;
# NET "F_DDR3_D[8]" LOC = N17;
# NET "F_DDR3_D[9]" LOC = N18;
# NET "F_DDR3_D[0]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[10]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[11]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[12]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[13]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[14]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[15]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[1]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[2]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[3]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[4]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[5]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[6]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[7]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[8]" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_D[9]" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_RST_N" LOC = F14;
# NET "F_DDR3_RST_N" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_ODT" LOC = K14;
# NET "F_DDR3_ODT" OUT_TERM = UNTUNED_50;

# NET "F_RAS_N" LOC = K15;
# NET "F_RAS_N" OUT_TERM = UNTUNED_50;
# NET "F_UDM" LOC = L15;
# NET "F_UDM" OUT_TERM = UNTUNED_50;
# NET "F_UDQS_N" LOC = N16;
# NET "F_UDQS_N" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_UDQS_N" OUT_TERM = UNTUNED_50;
# NET "F_UDQS_P" LOC = N15;
# NET "F_UDQS_P" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_UDQS_P" OUT_TERM = UNTUNED_50;
# NET "F_LDM" LOC = L16;
# NET "F_LDM" OUT_TERM = UNTUNED_50;
# NET "F_LDQS_N" LOC = K18;
# NET "F_LDQS_N" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_LDQS_N" OUT_TERM = UNTUNED_50;
# NET "F_LDQS_P" LOC = K17;
# NET "F_LDQS_P" IOSTANDARD = DIFF_SSTL15_II;
# NET "F_LDQS_P" OUT_TERM = UNTUNED_50;
# NET "F_WE_N" LOC = K12;
# NET "F_WE_N" OUT_TERM = UNTUNED_50;

# NET "F_DDR3_RZQ" LOC = F15;
# NET "F_DDR3_RZQ" OUT_TERM = UNTUNED_50;
# NET "F_DDR3_ZIO" LOC = M14;
# NET "F_DDR3_ZIO" OUT_TERM = UNTUNED_50;

#NET "F_BA[*]" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_CAS_N" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_DDR3_A[*]" SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_DDR3_CKE" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;


#NET "F_DDR3_D[*]" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_DDR3_RST_N" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;

#NET "F_DDR3_ODT" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_RAS_N" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET "F_UDM" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET "F_LDM" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET "F_WE_N" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

#NET "F_DDR3_RZQ" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET "F_DDR3_ZIO" IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;


##############
# I/O connector
##############
#NET "F_DX0" LOC = K6;
#NET "F_DX0" IOSTANDARD = LVCMOS33;
#NET "F_DX0" SLEW = SLOW;
# NET "F_DX0" PULLUP;

NET "F_DX1" LOC = L7;
NET "F_DX1" IOSTANDARD = LVCMOS33;
NET "F_DX1" SLEW = SLOW;

#NET "F_DX2" LOC = H3;
#NET "F_DX2" IOSTANDARD = LVCMOS33;
#NET "F_DX2" SLEW = SLOW;

NET "F_DX3" LOC = H4;
NET "F_DX3" IOSTANDARD = LVCMOS33;
NET "F_DX3" SLEW = SLOW;
# NET "F_DX3" PULLUP;

# NET "F_DX[4]" LOC = J1;
# NET "F_DX[5]" LOC = J3;
# NET "F_DX6" LOC = L3;
# NET "F_DX6" IOSTANDARD = LVCMOS33;
# NET "F_DX6" SLEW = SLOW;

NET "F_DX7" LOC = L4;
NET "F_DX7" IOSTANDARD = LVCMOS33;
NET "F_DX7" SLEW = SLOW;

# NET "F_DX8" LOC = K2;
# NET "F_DX8" IOSTANDARD = LVCMOS33;
# NET "F_DX8" SLEW = SLOW;

#NET "F_DX11" LOC = M1;
#NET "F_DX11" IOSTANDARD = LVCMOS33;
#NET "F_DX11" SLEW = SLOW;
# NET "F_DX12" LOC = M3;
# NET "F_DX12" IOSTANDARD = LVCMOS33;
# NET "F_DX12" SLEW = SLOW;

# NET "F_DX13" LOC = P2;
# NET "F_DX13" IOSTANDARD = LVCMOS33;
# NET "F_DX13" SLEW = SLOW;

# NET "F_DX14" LOC = T2;
# NET "F_DX14" IOSTANDARD = LVCMOS33;
# NET "F_DX14" SLEW = SLOW;

NET "F_DX15" LOC = M5;
NET "F_DX15" IOSTANDARD = LVCMOS33;
NET "F_DX15" SLEW = SLOW;

# NET "F_DX[16]" LOC = L6;
NET "F_DX17" LOC = G1;
NET "F_DX17" IOSTANDARD = LVCMOS33;
NET "F_DX17" SLEW = SLOW;
#NET "F_DX18" LOC = H7;
#NET "F_DX18" IOSTANDARD = LVCMOS33;
#NET "F_DX18" SLEW = SLOW;

# NET "F_DX[*]" IOSTANDARD = LVCMOS33;

NET "F_LVDS_N0" LOC = P6;
NET "F_LVDS_N0" IOSTANDARD = LVCMOS33;
NET "F_LVDS_N0" SLEW = SLOW;
NET "F_LVDS_P0" LOC = N5;
NET "F_LVDS_P0" IOSTANDARD = LVCMOS33;
NET "F_LVDS_P0" SLEW = SLOW;
# NET "F_LVDS_N1" LOC = V4;
# NET "F_LVDS_N1" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N1" SLEW = SLOW;
# NET "F_LVDS_P1" LOC = T4;
# NET "F_LVDS_P1" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_P1" SLEW = SLOW;
# NET "F_LVDS_N2" LOC = T3;
# NET "F_LVDS_N2" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N2" SLEW = SLOW;
# NET "F_LVDS_P[2]" LOC = R3;

# NET "F_LVDS_N3" LOC = V5;
# NET "F_LVDS_N3" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N3" SLEW = SLOW;

# NET "F_LVDS_P[3]" LOC = U5;
# NET "F_LVDS_N4" LOC = T5;
# NET "F_LVDS_N4" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N4" SLEW = SLOW;
NET "F_LVDS_P4" LOC = R5;
NET "F_LVDS_P4" IOSTANDARD = LVCMOS33;
NET "F_LVDS_P4" SLEW = SLOW;

# NET "F_LVDS_N5" LOC = T7;
# NET "F_LVDS_N5" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N5" SLEW = SLOW;

# NET "F_LVDS_P5" LOC = R7;
# NET "F_LVDS_P5" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_P5" SLEW = SLOW;

# NET "F_LVDS_N[6]" LOC = V6;
# NET "F_LVDS_P[6]" LOC = T6;
NET "F_LVDS_N7" LOC = V7;
NET "F_LVDS_N7" IOSTANDARD = LVCMOS33;
NET "F_LVDS_N7" SLEW = SLOW;

NET "F_LVDS_P7" LOC = U7;
NET "F_LVDS_P7" IOSTANDARD = LVCMOS33;
NET "F_LVDS_P7" SLEW = SLOW;

# NET "F_LVDS_N8" LOC = V8;
# NET "F_LVDS_N8" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N8" SLEW = SLOW;

# NET "F_LVDS_P[8]" LOC = U8;
# NET "F_LVDS_N[9]" LOC = V9;
#NET "F_LVDS_P9" LOC = T9;
#NET "F_LVDS_P9" IOSTANDARD = LVCMOS33;

# NET "F_LVDS_N[10]" LOC = V11;
# NET "F_LVDS_P[10]" LOC = U11;
NET "F_LVDS_N11" LOC = T11;
NET "F_LVDS_N11" IOSTANDARD = LVCMOS33;
NET "F_LVDS_N11" SLEW = SLOW;
NET "F_LVDS_P11" LOC = R11;
NET "F_LVDS_P11" IOSTANDARD = LVCMOS33;
NET "F_LVDS_P11" SLEW = SLOW;
# NET "F_LVDS_N[12]" LOC = V13;
# NET "F_LVDS_P[12]" LOC = U13;
# NET "F_LVDS_N[13]" LOC = V14;
# NET "F_LVDS_P[13]" LOC = T14;
# NET "F_LVDS_N[14]" LOC = V16;
# NET "F_LVDS_P[14]" LOC = U16;
NET "F_LVDS_N15" LOC = V10;
NET "F_LVDS_N15" IOSTANDARD = LVCMOS33;
NET "F_LVDS_N15" SLEW = SLOW;
NET "F_LVDS_P15" LOC = U10;
NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
NET "F_LVDS_P15" SLEW = SLOW;

# NET "F_LVDS_P[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_N[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;

# NET "F_LVDS_NA" LOC = K3;
# NET "F_LVDS_NA" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_PA" LOC = K4;
# NET "F_LVDS_PA" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_NB" LOC = K5;
# NET "F_LVDS_NB" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_NB" SLEW = SLOW;
# NET "F_LVDS_PB" LOC = L5;
# NET "F_LVDS_PB" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_PB" SLEW = SLOW;
NET "F_LVDS_NC" LOC = L1;
NET "F_LVDS_NC" IOSTANDARD = LVCMOS33;
NET "F_LVDS_NC" SLEW = SLOW;
# NET "F_LVDS_PC" LOC = L2;
# NET "F_LVDS_PC" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_PC" SLEW = SLOW;

#NET "F_LVDS_CK0_N" LOC = T8;
#NET "F_LVDS_CK0_N" IOSTANDARD = LVCMOS33;
#NET "F_LVDS_CK0_P" LOC = R8;
#NET "F_LVDS_CK0_P" IOSTANDARD = LVCMOS33;

NET "F_LVDS_CK1_N" LOC = T10;
NET "F_LVDS_CK1_N" IOSTANDARD = LVCMOS33;
NET "F_LVDS_CK1_N" SLEW = SLOW;
NET "F_LVDS_CK1_P" LOC = R10;
NET "F_LVDS_CK1_P" IOSTANDARD = LVCMOS33;
NET "F_LVDS_CK1_P" SLEW = SLOW;

# NET "F_LVDS_CK_N[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_CK_P[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
NET "CLK2_P" PERIOD = 20 ns;