aboutsummaryrefslogtreecommitdiff
path: root/rtl/src/verilog/novena_baseline_top.v
blob: a62f311f804b1e216de2071c47edbacc889689e1 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
`timescale 1ns / 1ps

module novena_baseline_top
	(
		gclk_p_pin, gclk_n_pin,

		eim_bclk, eim_cs0_n, eim_da,
		eim_lba_n, eim_wr_n,
		eim_oe_n, eim_wait_n,

		reset_mcu_b_pin,
		apoptosis_pin,
		led_pin
	);
	
		//
		// Top-Levl Ports
		//
	input		wire				gclk_p_pin;			// general-purpose 50 MHz LVDS clock 
	input		wire				gclk_n_pin;			//

	input		wire				eim_bclk;			// burst clock from cpu
	input		wire				eim_cs0_n;			// chip select (active low)
	inout		wire	[15: 0]	eim_da;				// bi-directional address/data bus
	input		wire				eim_lba_n;			// latch address signal (active low)
	input		wire				eim_wr_n;			// write enable signal (active low)
	input		wire				eim_oe_n;			// output enable signal (active low)
	output	wire				eim_wait_n;			// wait signal (active low)

	input		wire				reset_mcu_b_pin;	// this must be configured as input w/pullup
															// not to kill the cpu after configuration
	output	wire				apoptosis_pin;		// not used, tied to 0
	output	wire				led_pin;				// visual activity indicator
	

		//
		// Clock Manager
		//
		
		/* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */
		
	wire	sys_clk;
	wire	sys_rst;
	
	wire	eim_bclk_buf;
	
	novena_clkmgr clkmgr
	(
		.gclk_p			(gclk_p_pin),
		.gclk_n			(gclk_n_pin),
		
		.reset_mcu_b	(reset_mcu_b_pin),
		
		.sys_clk			(sys_clk),
		.sys_rst			(sys_rst),
		
		.bclk_in			(eim_bclk),
		.bclk_out		(eim_bclk_buf)
	);
	
	
		//
		// EIM Arbiter
		//
		
		/* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */

	wire	[13: 0]	sys_eim_addr;
	wire				sys_eim_wr;
	wire				sys_eim_rd;
	wire	[31: 0]	sys_eim_dout;
	wire	[31: 0]	sys_eim_din;	

	eim_arbiter eim
	(
		.eim_bclk		(eim_bclk_buf),
		.eim_cs0_n		(eim_cs0_n),
		.eim_da			(eim_da),
		.eim_lba_n		(eim_lba_n),
		.eim_wr_n		(eim_wr_n),
		.eim_oe_n		(eim_oe_n),
		.eim_wait_n		(eim_wait_n),

		.sys_clk			(sys_clk),
		
		.sys_addr		(sys_eim_addr),
		.sys_wren		(sys_eim_wr),
		.sys_data_out	(sys_eim_dout),
		.sys_rden		(sys_eim_rd),
		.sys_data_in	(sys_eim_din)
	);
	
	
		//
		// Core Selector (MUX)
		//
		
		/* This multiplexor is used to map demo adder registers somewhere into EIM address space. */
		
	core_selector mux
	(
		.sys_clk			(sys_clk),
		.sys_rst			(sys_rst),
		
		.sys_eim_addr	(sys_eim_addr),
		.sys_eim_wr		(sys_eim_wr),
		.sys_eim_rd		(sys_eim_rd),
		
		.sys_eim_dout	(sys_eim_dout),
		.sys_eim_din	(sys_eim_din)
	);
	
	
		//
		// LED Driver
		//
	eim_indicator led
	(
		.sys_clk			(sys_clk),
		.sys_rst			(sys_rst),
		.eim_active		(sys_eim_wr | sys_eim_rd),
		.led_out			(led_pin)
	);
	
	
		//
		// Unused
		//
	assign apoptosis_pin		= 1'b0;
	
	
endmodule