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//======================================================================
//
// demo_adder.v
// ------------
// Simple test core for the Cryptech Novena FPGA framework. The core
// s a 32-bit adder that allows us to verfy that we can write registers
// get a computation done and read out the registers via the EIM.
//
//
// Author: Pavel Shatov
// Copyright (c) 2014, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module demo_adder
(
clk, rst,
x, y, z,
ctl, sts
);
//
// Ports
//
input wire clk; // clock
input wire rst; // reset
input wire [31: 0] x; // x
input wire [31: 0] y; // y
output wire [31: 0] z; // z = x + y
input wire [15: 0] ctl; // control
output wire [15: 0] sts; // status
//
// Internal Registers
//
reg [31: 0] z_reg = {32{1'b0}};
reg [15: 0] sts_reg = {16{1'b0}};
reg [15: 0] ctl_dly = {16{1'b0}};
assign z = z_reg;
assign sts = sts_reg;
//
// Control Logic
//
always @(posedge clk)
//
if (rst) ctl_dly <= {16{1'b0}};
else ctl_dly <= ctl;
/* This flag is set whenever different value is written to control register. */
wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0;
//
// Adder Logic
//
always @(posedge clk)
//
if (rst) z_reg <= {32{1'b0}};
else if (adder_go) z_reg <= x + y;
//
// Status Logic
//
always @(posedge clk)
//
if (rst) sts_reg <= {16{1'b0}};
else if (adder_go) sts_reg <= ctl;
endmodule
//======================================================================
// EOF demo_adder.v
//======================================================================
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