//======================================================================
//
// core_selector.v
// ---------------
// Core selector Cryptech Novena FPGA framework.
//
//
// Author: Pavel Shatov
// Copyright (c) 2014, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
//   be used to endorse or promote products derived from this software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================

module core_selector
	(
	 input wire           sys_clk,
         input wire           sys_rst,

	 input wire [13: 0]   sys_eim_addr,
         input wire           sys_eim_wr,
         input wire           sys_eim_rd,
         output wire [31 : 0] read_data,
	 input wire [31 : 0]  write_data
	);


  //
  // Parameters
  //
  localparam	ADDER_BASE_ADDR		= 6'h00;	// upper 6 bits of address
  localparam	ADDER_OFFSET_X_REG	= 8'h00;	// X
  localparam	ADDER_OFFSET_Y_REG	= 8'h01;	// Y


  /* This flag detects whether adder core is being addressed. */
  wire eim_access_adder	= (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;

  /* These flags detect whether write or read access is requested. */
  wire eim_access_write	= sys_eim_wr & eim_access_adder;
  wire eim_access_read	= sys_eim_rd & eim_access_adder;
  wire select = eim_access_read | eim_access_write;

//  reg [31 : 0] read_data_reg;
//  reg [31 : 0] y_reg;
//  reg [31 : 0] x_reg;
//
//  //
//  // Write Request Handler
//  //
//  always @(posedge sys_clk)
//    //
//    if (sys_rst) begin
//      x_reg <= 32'hdeaddead;
//      y_reg <= 32'hbeefbeef;
//  end
//    else if (eim_access_write) begin
//      case (sys_eim_addr[7:0])
//        ADDER_OFFSET_X_REG:  x_reg <= write_data;
//        ADDER_OFFSET_Y_REG:  y_reg <= write_data;
//      endcase
//    end
//
//
//  //
//  // Read Request Handler
//  always @(posedge sys_clk)
//    //
//    if (sys_rst)
//      read_data_reg <= 32'h00000000;
//    //
//    else if (eim_access_read) begin
//      //
//      case (sys_eim_addr[7:0])
//	ADDER_OFFSET_X_REG:	read_data_reg	<= x_reg;
//	ADDER_OFFSET_Y_REG:	read_data_reg	<= y_reg;
//      endcase
//      //
//    end

//    assign read_data = read_data_reg;


    //  localparam SHA256_BASE_ADDR = 6'h14;
    //
    //  wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0;
    //  wire read_access   = sys_eim_rd & access_sha256;
    //  wire write_access  = sys_eim_wr & access_sha256;
    //  wire select        = read_access | write_access;

//  reg [31 : 0] read_data_reg;
//  wire  [31 : 0] sha_read_data;
//
//  assign read_data = read_data_reg;
//
//  always @ (posedge sys_clk)
//    begin
//      if (sys_rst)
//        begin
//          read_data_reg <= 32'h00000000;
//        end
//      else
//        begin
//          read_data_reg <= sha_read_data;
//        end
//    end


  sha256 sha256_inst(
                     .clk(sys_clk),
                     .reset_n(1'b1),

                     .cs(eim_access_adder),
                     .we(sys_eim_wr),

                     .address(sys_eim_addr[7 : 0]),
                     .write_data(write_data),
                     .read_data(read_data),
                     .error()
                    );

endmodule

//======================================================================
// EOF core_selector.v
//======================================================================