#====================================================================== # # novena_baseline.ucf # ------------------- # Constraint file for implementing the Cryptech Novena base # for the Xilinx Spartan6 LX45 on the Novena. # # # Author: Pavel Shatov # Copyright (c) 2014, NORDUnet A/S All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # - Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # # - Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # - Neither the name of the NORDUnet nor the names of its contributors may # be used to endorse or promote products derived from this software # without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A # PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED # TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #====================================================================== #------------------------------------------------------------------------------- CONFIG VCCAUX = 3.3; #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------- # GCLK Timing #-------------------------------------------------------------------------------- NET "gclk_p_pin" TNM_NET = TNM_gclk; TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%; #------------------------------------------------------------------------------- # BCLK Timing #------------------------------------------------------------------------------- NET "eim_bclk" TNM_NET = TNM_bclk; TIMESPEC TS_bclk = PERIOD TNM_bclk 30 ns HIGH 50%; #------------------------------------------------------------------------------- # FPGA Pinout #------------------------------------------------------------------------------- NET "led_pin" LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12; NET "apoptosis_pin" LOC = "K1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12; NET "reset_mcu_b_pin" LOC = "F1" | IOSTANDARD = "LVCMOS33" | PULLUP; NET "gclk_p_pin" LOC = "H2" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE"; NET "gclk_n_pin" LOC = "H1" | IOSTANDARD = "LVDS_33" | DIFF_TERM = "TRUE"; NET "eim_bclk" LOC = "C9" | IOSTANDARD = "LVCMOS33"; NET "eim_cs0_n" LOC = "B11" | IOSTANDARD = "LVCMOS33"; NET "eim_da<0>" LOC = "G9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<1>" LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<2>" LOC = "F9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<3>" LOC = "B9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<4>" LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<5>" LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<6>" LOC = "A9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<7>" LOC = "A8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<8>" LOC = "B8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<9>" LOC = "D8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<10>" LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<11>" LOC = "C8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<13>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<14>" LOC = "C4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_da<15>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; NET "eim_lba_n" LOC = "B14" | IOSTANDARD = "LVCMOS33"; NET "eim_wr_n" LOC = "C14" | IOSTANDARD = "LVCMOS33"; NET "eim_oe_n" LOC = "C10" | IOSTANDARD = "LVCMOS33"; NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12; # Pins to the header where the LEDs on the Cryptech # Avalanche Noise Board are connected. NET "ct_led[0]" LOC = K6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[1]" LOC = H4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[2]" LOC = H3 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[3]" LOC = M1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[4]" LOC = L7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[5]" LOC = G1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[6]" LOC = T2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; NET "ct_led[7]" LOC = H7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; # Pins to the header where the noise sources on the # Cryptech Avalanche Noise Board are connected. # Rev 02 schmitt-triggered source. NET "ct_noise" | LOC = L4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; # Rev 02 non schmitt-triggered source. Not used right now. # Left here as documentation. #NET "ct_noise_F_DX15" | LOC = M5 | IOSTANDARD = LVCMOS33 | SLEW = SLOW; #------------------------------------------------------------------------------- # EIM Input Timing #------------------------------------------------------------------------------- NET "eim_cs0_n" TNM = "TNM_EIM_IN"; NET "eim_da<*>" TNM = "TNM_EIM_IN"; NET "eim_lba_n" TNM = "TNM_EIM_IN"; NET "eim_wr_n" TNM = "TNM_EIM_IN"; NET "eim_oe_n" TNM = "TNM_EIM_IN"; TIMEGRP "TNM_EIM_IN" OFFSET = IN 9.75 ns VALID 16.0 ns BEFORE "eim_bclk" RISING; #------------------------------------------------------------------------------- # EIM Output Timing #------------------------------------------------------------------------------- NET "eim_da<*>" TNM = "TNM_EIM_OUT"; NET "eim_wait_n" TNM = "TNM_EIM_OUT"; TIMEGRP "TNM_EIM_OUT" OFFSET = OUT 13.0 ns AFTER "eim_bclk" FALLING; #------------------------------------------------------------------------------- # CDC Paths #------------------------------------------------------------------------------- INST "eim/eim_cdc/cdc_eim_sys/src_ff" TNM = "TNM_from_bclk"; INST "eim/eim_cdc/cdc_eim_sys/src_latch*" TNM = "TNM_from_bclk"; INST "eim/eim_cdc/cdc_eim_sys/ff_sync*" TNM = "TNM_to_sys_clk"; INST "eim/eim_cdc/cdc_eim_sys/dst_latch*" TNM = "TNM_to_sys_clk"; INST "eim/eim_cdc/cdc_sys_eim/src_ff" TNM = "TNM_from_sys_clk"; INST "eim/eim_cdc/cdc_sys_eim/src_latch*" TNM = "TNM_from_sys_clk"; INST "eim/eim_cdc/cdc_sys_eim/ff_sync*" TNM = "TNM_to_bclk"; INST "eim/eim_cdc/cdc_sys_eim/dst_latch*" TNM = "TNM_to_bclk"; TIMESPEC "TS_bclk_2_sys_clk" = FROM "TNM_from_bclk" TO "TNM_to_sys_clk" TIG; TIMESPEC "TS_sys_clk_2_bclk" = FROM "TNM_from_sys_clk" TO "TNM_to_bclk" TIG; #====================================================================== # EOF novena_baseline.ucf #======================================================================