Analyzing Verilog file "Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v" into library work 3'/> Unnamed repository; edit this file 'description' to name the repository.git repositories
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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-05-25 09:29:03 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-05-25 09:29:58 +0300
commit5f70a0d7f7c59c73ab3050f80a911962b4c53df3 (patch)
tree206ef0c5a4bb624ca3f420a6dcaabf121a91458f /KiCAD
parent806f4dbc3bf683bd7be3a47c3e119abfb6dd0af1 (diff)
Internal signal layer #1 cleaned up.
Diffstat (limited to 'KiCAD')