Generating IP... A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis Finished generation of ASY schematic symbol. Finished FLIST file generation.