From 7a9e34eadc7db72f43d2566d0595e7de5e4a18ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 31 Jan 2015 08:58:23 +0100 Subject: Adding initial version of the sw parts of the baseline. --- sw/test-adder/novena-eim.h | 297 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) create mode 100755 sw/test-adder/novena-eim.h (limited to 'sw/test-adder/novena-eim.h') diff --git a/sw/test-adder/novena-eim.h b/sw/test-adder/novena-eim.h new file mode 100755 index 0000000..fdcf5a5 --- /dev/null +++ b/sw/test-adder/novena-eim.h @@ -0,0 +1,297 @@ +//------------------------------------------------------------------------------ +// novena-eim.h +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Defined Values +//------------------------------------------------------------------------------ +#define MEMORY_DEVICE "/dev/mem" + + +//------------------------------------------------------------------------------ +// IOMUXC Values +//------------------------------------------------------------------------------ +#define IOMUXC_MUX_MODE_ALT0 0 // 000 + +#define IOMUXC_PAD_CTL_SRE_FAST 1 // 1 +#define IOMUXC_PAD_CTL_DSE_33_OHM 7 // 111 +#define IOMUXC_PAD_CTL_SPEED_MEDIUM_10 2 // 10 +#define IOMUXC_PAD_CTL_ODE_DISABLED 0 // 0 +#define IOMUXC_PAD_CTL_PKE_DISABLED 0 // 0 +#define IOMUXC_PAD_CTL_PUE_PULL 1 // 1 +#define IOMUXC_PAD_CTL_PUS_100K_OHM_PU 2 // 10 +#define IOMUXC_PAD_CTL_HYS_DISABLED 0 // 0 + +//------------------------------------------------------------------------------ +// CCM Values +//------------------------------------------------------------------------------ +#define CCM_CGR_OFF 0 // 00 +#define CCM_CGR_ON_EXCEPT_STOP 3 // 11 + + +//------------------------------------------------------------------------------ +// CPU Registers +//------------------------------------------------------------------------------ +enum IMX6DQ_REGISTER_OFFSET +{ + IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0x020E00F8, + IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0x020E0100, + IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0x020E0104, + IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0x020E0108, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 = 0x020E0114, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 = 0x020E0118, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 = 0x020E011C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 = 0x020E0120, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 = 0x020E0124, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 = 0x020E0128, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 = 0x020E012C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 = 0x020E0130, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 = 0x020E0134, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 = 0x020E0138, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 = 0x020E013C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 = 0x020E0140, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 = 0x020E0144, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 = 0x020E0148, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 = 0x020E014C, + IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 = 0x020E0150, + IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B = 0x020E0154, + IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK = 0x020E0158, + + IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B = 0x020E040C, + IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B = 0x020E0414, + IOMUXC_SW_PAD_CTL_PAD_EIM_RW = 0x020E0418, + IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B = 0x020E041C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 = 0x020E0428, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 = 0x020E042C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 = 0x020E0430, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 = 0x020E0434, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 = 0x020E0438, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 = 0x020E043C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 = 0x020E0440, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 = 0x020E0444, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 = 0x020E0448, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 = 0x020E044C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 = 0x020E0450, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 = 0x020E0454, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 = 0x020E0458, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 = 0x020E045C, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 = 0x020E0460, + IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 = 0x020E0464, + IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B = 0x020E0468, + IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK = 0x020E046C, + + CCM_CCGR6 = 0x020C4080, + + EIM_CS0GCR1 = 0x021B8000, + EIM_CS0GCR2 = 0x021B8004, + EIM_CS0RCR1 = 0x021B8008, + EIM_CS0RCR2 = 0x021B800C, + EIM_CS0WCR1 = 0x021B8010, + EIM_CS0WCR2 = 0x021B8014, + + EIM_WCR = 0x021B8090, + EIM_WIAR = 0x021B8094, + EIM_EAR = 0x021B8098, + + EIM_BASE_ADDR = 0x08000000 +}; + + +//------------------------------------------------------------------------------ +struct IOMUXC_SW_MUX_CTL_PAD_EIM +//------------------------------------------------------------------------------ +{ + unsigned int mux_mode : 3; + unsigned int reserved_3 : 1; + unsigned int sion : 1; + unsigned int reserved_31_5 : 27; +}; +//------------------------------------------------------------------------------ +struct IOMUXC_SW_PAD_CTL_PAD_EIM +//------------------------------------------------------------------------------ +{ + unsigned int sre : 1; + unsigned int reserved_2_1 : 2; + unsigned int dse : 3; + unsigned int speed : 2; + unsigned int reserved_10_8 : 3; + unsigned int ode : 1; + unsigned int pke : 1; + unsigned int pue : 1; + unsigned int pus : 2; + unsigned int hys : 1; + unsigned int reserved_31_17 : 15; +}; + + +//------------------------------------------------------------------------------ +struct CCM_CCGR6 +//------------------------------------------------------------------------------ +{ + unsigned int cg0_usboh3 : 2; + unsigned int cg1_usdhc1 : 2; + unsigned int cg2_usdhc2 : 2; + unsigned int cg3_usdhc3 : 2; + + unsigned int cg3_usdhc4 : 2; + unsigned int cg5_eim_slow : 2; + unsigned int cg6_vdoaxiclk : 2; + unsigned int cg7_vpu : 2; + + unsigned int cg8_reserved : 2; + unsigned int cg9_reserved : 2; + unsigned int cg10_reserved : 2; + unsigned int cg11_reserved : 2; + + unsigned int cg12_reserved : 2; + unsigned int cg13_reserved : 2; + unsigned int cg14_reserved : 2; + unsigned int cg15_reserved : 2; +}; + + +//------------------------------------------------------------------------------ +struct EIM_CS_GCR1 +//------------------------------------------------------------------------------ +{ + unsigned int csen : 1; + unsigned int swr : 1; + unsigned int srd : 1; + unsigned int mum : 1; + unsigned int wfl : 1; + unsigned int rfl : 1; + unsigned int cre : 1; + unsigned int crep : 1; + unsigned int bl : 3; + unsigned int wc : 1; + unsigned int bcd : 2; + unsigned int bcs : 2; + unsigned int dsz : 3; + unsigned int sp : 1; + unsigned int csrec : 3; + unsigned int aus : 1; + unsigned int gbc : 3; + unsigned int wp : 1; + unsigned int psz : 4; +}; +//------------------------------------------------------------------------------ +struct EIM_CS_GCR2 +//------------------------------------------------------------------------------ +{ + unsigned int adh : 2; + unsigned int reserved_3_2 : 2; + unsigned int daps : 4; + unsigned int dae : 1; + unsigned int dap : 1; + unsigned int reserved_11_10 : 2; + unsigned int mux16_byp_grant : 1; + unsigned int reserved_31_13 : 19; +}; +//------------------------------------------------------------------------------ +struct EIM_CS_RCR1 +//------------------------------------------------------------------------------ +{ + unsigned int rcsn : 3; + unsigned int reserved_3 : 1; + unsigned int rcsa : 3; + unsigned int reserved_7 : 1; + unsigned int oen : 3; + unsigned int reserved_11 : 1; + unsigned int oea : 3; + unsigned int reserved_15 : 1; + unsigned int radvn : 3; + unsigned int ral : 1; + unsigned int radva : 3; + unsigned int reserved_23 : 1; + unsigned int rwsc : 6; + unsigned int reserved_31_30 : 2; +}; +//------------------------------------------------------------------------------ +struct EIM_CS_RCR2 +//------------------------------------------------------------------------------ +{ + unsigned int rben : 3; + unsigned int rbe : 1; + unsigned int rbea : 3; + unsigned int reserved_7 : 1; + unsigned int rl : 2; + unsigned int reserved_11_10 : 2; + unsigned int pat : 3; + unsigned int apr : 1; + unsigned int reserved_31_16 : 16; +}; +//------------------------------------------------------------------------------ +struct EIM_CS_WCR1 +//------------------------------------------------------------------------------ +{ + unsigned int wcsn : 3; + unsigned int wcsa : 3; + unsigned int wen : 3; + unsigned int wea : 3; + unsigned int wben : 3; + unsigned int wbea : 3; + unsigned int wadvn : 3; + unsigned int wadva : 3; + unsigned int wwsc : 6; + unsigned int wbed : 1; + unsigned int wal : 1; +}; +//------------------------------------------------------------------------------ +struct EIM_CS_WCR2 +//------------------------------------------------------------------------------ +{ + unsigned int wbcdd : 1; + unsigned int reserved_31_1 : 31; +}; +//------------------------------------------------------------------------------ +struct EIM_WCR +//------------------------------------------------------------------------------ +{ + unsigned int bcm : 1; + unsigned int gbcd : 2; + unsigned int reserved_3 : 1; + unsigned int inten : 1; + unsigned int intpol : 1; + unsigned int reserved_7_6 : 2; + unsigned int wdog_en : 1; + unsigned int wdog_limit : 2; + unsigned int reserved_31_11 : 21; +}; +//------------------------------------------------------------------------------ +struct EIM_WIAR +//------------------------------------------------------------------------------ +{ + unsigned int ips_req : 1; + unsigned int ips_ack : 1; + unsigned int irq : 1; + unsigned int errst : 1; + unsigned int aclk_en : 1; + unsigned int reserved_31_5 : 27; +}; +//------------------------------------------------------------------------------ +struct EIM_EAR +//------------------------------------------------------------------------------ +{ + unsigned int error_addr : 32; +}; + + +//------------------------------------------------------------------------------ +// Prototypes +//------------------------------------------------------------------------------ +int eim_setup (); +void eim_write_32 (off_t, unsigned int *); +void eim_read_32 (off_t, unsigned int *); + +void _eim_setup_iomuxc (); +void _eim_setup_ccm (); +void _eim_setup_eim (); +void _eim_cleanup (); +off_t _eim_calc_offset (off_t); +void _eim_remap_mem (off_t); + + +//------------------------------------------------------------------------------ +// End-of-File +//------------------------------------------------------------------------------ -- cgit v1.2.3