From d88592bf59eeb7263507f4d13a69aa841840bda7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sun, 1 Feb 2015 09:36:44 +0100 Subject: Added proper file headers to all verilog source files. --- rtl/src/verilog/cdc_bus_pulse.v | 52 ++++++- rtl/src/verilog/core_selector.v | 42 +++++- rtl/src/verilog/demo_adder.v | 174 ++++++++++++++--------- rtl/src/verilog/eim_arbiter.v | 43 +++++- rtl/src/verilog/eim_arbiter_cdc.v | 253 ++++++++++++++++++++-------------- rtl/src/verilog/eim_da_phy.v | 42 +++++- rtl/src/verilog/eim_indicator.v | 112 ++++++++++----- rtl/src/verilog/novena_baseline_top.v | 44 +++++- rtl/src/verilog/novena_clkmgr.v | 43 +++++- 9 files changed, 586 insertions(+), 219 deletions(-) (limited to 'rtl/src/verilog') diff --git a/rtl/src/verilog/cdc_bus_pulse.v b/rtl/src/verilog/cdc_bus_pulse.v index 631506c..6f1fa34 100644 --- a/rtl/src/verilog/cdc_bus_pulse.v +++ b/rtl/src/verilog/cdc_bus_pulse.v @@ -1,4 +1,45 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// cdc_bus_pulse.v +// --------------- +// Clock Domain Crossing handler for the Cryptech Novena +// FPGA framework design. +// +// This module is based on design suggested on page 27 of the +// paper 'Clock Domain Crossing (CDC) Design & Verification Techniques +// Using SystemVerilog' by Clifford E. Cummings (Sunburst Design, Inc.) +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module cdc_bus_pulse ( @@ -6,11 +47,6 @@ module cdc_bus_pulse dst_clk, dst_dout, dst_pulse ); - /* This module is based on design suggested on page 27 of an article titled - "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog" - by Clifford E. Cummings (Sunburst Design, Inc.) - */ - // // Parameters // @@ -112,3 +148,7 @@ module cdc_bus_pulse endmodule + +//====================================================================== +// EOF cdc_bus_pulse.v +//====================================================================== diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index eb6551a..629d3b6 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,4 +1,40 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// core_selector.v +// --------------- +// Core selector Cryptech Novena FPGA framework. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module core_selector ( @@ -110,3 +146,7 @@ module core_selector endmodule + +//====================================================================== +// EOF core_selector.v +//====================================================================== diff --git a/rtl/src/verilog/demo_adder.v b/rtl/src/verilog/demo_adder.v index a86f114..54e7f72 100644 --- a/rtl/src/verilog/demo_adder.v +++ b/rtl/src/verilog/demo_adder.v @@ -1,66 +1,108 @@ -`timescale 1ns / 1ps - -module demo_adder - ( - clk, rst, - x, y, z, - ctl, sts - ); - - // - // Ports - // - input wire clk; // clock - input wire rst; // reset - - input wire [31: 0] x; // x - input wire [31: 0] y; // y - output wire [31: 0] z; // z = x + y - - input wire [15: 0] ctl; // control - output wire [15: 0] sts; // status - - - // - // Internal Registers - // - reg [31: 0] z_reg = {32{1'b0}}; - reg [15: 0] sts_reg = {16{1'b0}}; - reg [15: 0] ctl_dly = {16{1'b0}}; - - assign z = z_reg; - assign sts = sts_reg; - - - // - // Control Logic - // - always @(posedge clk) - // - if (rst) ctl_dly <= {16{1'b0}}; - else ctl_dly <= ctl; - - /* This flag is set whenever different value is written to control register. */ - - wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0; - - - // - // Adder Logic - // - always @(posedge clk) - // - if (rst) z_reg <= {32{1'b0}}; - else if (adder_go) z_reg <= x + y; - - - // - // Status Logic - // - always @(posedge clk) - // - if (rst) sts_reg <= {16{1'b0}}; - else if (adder_go) sts_reg <= ctl; - - -endmodule +//====================================================================== +// +// demo_adder.v +// ------------ +// Simple test core for the Cryptech Novena FPGA framework. The core +// s a 32-bit adder that allows us to verfy that we can write registers +// get a computation done and read out the registers via the EIM. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module demo_adder + ( + clk, rst, + x, y, z, + ctl, sts + ); + + // + // Ports + // + input wire clk; // clock + input wire rst; // reset + + input wire [31: 0] x; // x + input wire [31: 0] y; // y + output wire [31: 0] z; // z = x + y + + input wire [15: 0] ctl; // control + output wire [15: 0] sts; // status + + + // + // Internal Registers + // + reg [31: 0] z_reg = {32{1'b0}}; + reg [15: 0] sts_reg = {16{1'b0}}; + reg [15: 0] ctl_dly = {16{1'b0}}; + + assign z = z_reg; + assign sts = sts_reg; + + + // + // Control Logic + // + always @(posedge clk) + // + if (rst) ctl_dly <= {16{1'b0}}; + else ctl_dly <= ctl; + + /* This flag is set whenever different value is written to control register. */ + + wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0; + + + // + // Adder Logic + // + always @(posedge clk) + // + if (rst) z_reg <= {32{1'b0}}; + else if (adder_go) z_reg <= x + y; + + + // + // Status Logic + // + always @(posedge clk) + // + if (rst) sts_reg <= {16{1'b0}}; + else if (adder_go) sts_reg <= ctl; + + +endmodule + +//====================================================================== +// EOF demo_adder.v +//====================================================================== diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v index 1e39629..3dc6260 100644 --- a/rtl/src/verilog/eim_arbiter.v +++ b/rtl/src/verilog/eim_arbiter.v @@ -1,4 +1,41 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// eim_arbiter.v +// ------------- +// Port arbiter for the EIM interface for the Cryptech +// Novena FPGA framework. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module eim_arbiter ( @@ -245,3 +282,7 @@ module eim_arbiter endmodule + +//====================================================================== +// EOF eim_arbiter.v +//====================================================================== diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v index 6a60552..c9df62e 100644 --- a/rtl/src/verilog/eim_arbiter_cdc.v +++ b/rtl/src/verilog/eim_arbiter_cdc.v @@ -1,106 +1,147 @@ -`timescale 1ns / 1ps - -module eim_arbiter_cdc - ( - eim_clk, eim_req, eim_ack, eim_din, eim_dout, - sys_clk, sys_addr, - sys_wren, sys_data_out, - sys_rden, sys_data_in - ); - - - input wire eim_clk; // eim clock - input wire eim_req; // eim transaction request - output wire eim_ack; // eim transaction acknowledge - input wire [47: 0] eim_din; // data from cpu to fpga (write access) - output wire [31: 0] eim_dout; // data from fpga to cpu (read access) - - input wire sys_clk; // user internal clock - output wire [13: 0] sys_addr; // user access address - output wire sys_wren; // user write flag - output wire [31: 0] sys_data_out; // user write data - output wire sys_rden; // user read flag - input wire [31: 0] sys_data_in; // user read data - - - // - // EIM_CLK -> SYS_CLK Request - // - wire sys_req; // request pulse in sys_clk clock domain - wire [47: 0] sys_dout; // transaction data in sys_clk clock domain - - cdc_bus_pulse # - ( - .DATA_WIDTH (48) // {write, read, addr, data} - ) - cdc_eim_sys - ( - .src_clk (eim_clk), - .src_din (eim_din), - .src_req (eim_req), - - .dst_clk (sys_clk), - .dst_dout (sys_dout), - .dst_pulse (sys_req) - ); - - - // - // Output Registers - // - reg [13: 0] sys_addr_reg = {14{1'bX}}; // - reg sys_wren_reg = 1'b0; // - reg [31: 0] sys_data_out_reg = {32{1'bX}}; // - reg sys_rden_reg = 1'b0; // - - assign sys_addr = sys_addr_reg; - assign sys_wren = sys_wren_reg; - assign sys_data_out = sys_data_out_reg; - assign sys_rden = sys_rden_reg; - - - // - // System (User) Clock Access Handler - // - always @(posedge sys_clk) - // - if (sys_req) begin // request detected? - sys_wren_reg <= sys_dout[47]; // set write flag if needed - sys_addr_reg <= sys_dout[45:32]; // set operation address - sys_data_out_reg <= sys_dout[31: 0]; // set data to write - sys_rden_reg <= sys_dout[46]; // set read flag if needed - end else begin // no request active - sys_wren_reg <= 1'b0; // clear write flag - sys_rden_reg <= 1'b0; // clear read flag - end - - - // - // System Request 2-cycle delay to compensate registered mux delay in user-side logic - // - reg [ 1: 0] sys_req_dly = 2'b00; - - always @(posedge sys_clk) - sys_req_dly <= {sys_req_dly[0], sys_req}; - - - // - // SYS_CLK -> EIM_CLK Acknowledge - // - cdc_bus_pulse # - ( - .DATA_WIDTH (32) // {data} - ) - cdc_sys_eim - ( - .src_clk (sys_clk), - .src_din (sys_data_in), - .src_req (sys_req_dly[1]), - - .dst_clk (eim_clk), - .dst_dout (eim_dout), - .dst_pulse (eim_ack) - ); - - -endmodule +//====================================================================== +// +// eim_arbiter_cdc.v +// ----------------- +// The actual clock domain crossing handler od the EIM arbiter +// for the Cryptech Novena FPGA framework. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module eim_arbiter_cdc + ( + eim_clk, eim_req, eim_ack, eim_din, eim_dout, + sys_clk, sys_addr, + sys_wren, sys_data_out, + sys_rden, sys_data_in + ); + + + input wire eim_clk; // eim clock + input wire eim_req; // eim transaction request + output wire eim_ack; // eim transaction acknowledge + input wire [47: 0] eim_din; // data from cpu to fpga (write access) + output wire [31: 0] eim_dout; // data from fpga to cpu (read access) + + input wire sys_clk; // user internal clock + output wire [13: 0] sys_addr; // user access address + output wire sys_wren; // user write flag + output wire [31: 0] sys_data_out; // user write data + output wire sys_rden; // user read flag + input wire [31: 0] sys_data_in; // user read data + + + // + // EIM_CLK -> SYS_CLK Request + // + wire sys_req; // request pulse in sys_clk clock domain + wire [47: 0] sys_dout; // transaction data in sys_clk clock domain + + cdc_bus_pulse # + ( + .DATA_WIDTH (48) // {write, read, addr, data} + ) + cdc_eim_sys + ( + .src_clk (eim_clk), + .src_din (eim_din), + .src_req (eim_req), + + .dst_clk (sys_clk), + .dst_dout (sys_dout), + .dst_pulse (sys_req) + ); + + + // + // Output Registers + // + reg [13: 0] sys_addr_reg = {14{1'bX}}; // + reg sys_wren_reg = 1'b0; // + reg [31: 0] sys_data_out_reg = {32{1'bX}}; // + reg sys_rden_reg = 1'b0; // + + assign sys_addr = sys_addr_reg; + assign sys_wren = sys_wren_reg; + assign sys_data_out = sys_data_out_reg; + assign sys_rden = sys_rden_reg; + + + // + // System (User) Clock Access Handler + // + always @(posedge sys_clk) + // + if (sys_req) begin // request detected? + sys_wren_reg <= sys_dout[47]; // set write flag if needed + sys_addr_reg <= sys_dout[45:32]; // set operation address + sys_data_out_reg <= sys_dout[31: 0]; // set data to write + sys_rden_reg <= sys_dout[46]; // set read flag if needed + end else begin // no request active + sys_wren_reg <= 1'b0; // clear write flag + sys_rden_reg <= 1'b0; // clear read flag + end + + + // + // System Request 2-cycle delay to compensate registered mux delay in user-side logic + // + reg [ 1: 0] sys_req_dly = 2'b00; + + always @(posedge sys_clk) + sys_req_dly <= {sys_req_dly[0], sys_req}; + + + // + // SYS_CLK -> EIM_CLK Acknowledge + // + cdc_bus_pulse # + ( + .DATA_WIDTH (32) // {data} + ) + cdc_sys_eim + ( + .src_clk (sys_clk), + .src_din (sys_data_in), + .src_req (sys_req_dly[1]), + + .dst_clk (eim_clk), + .dst_dout (eim_dout), + .dst_pulse (eim_ack) + ); + + +endmodule + +//====================================================================== +// EOF eim_arbiter_cdc.v +//====================================================================== diff --git a/rtl/src/verilog/eim_da_phy.v b/rtl/src/verilog/eim_da_phy.v index 9b76d3b..9ef6042 100644 --- a/rtl/src/verilog/eim_da_phy.v +++ b/rtl/src/verilog/eim_da_phy.v @@ -1,4 +1,40 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// eim_da_phy.v +// ------------ +// IO buffer module for the EIM DA port. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module eim_da_phy ( @@ -45,3 +81,7 @@ module eim_da_phy endgenerate endmodule + +//====================================================================== +// EOF eim_da_phy.v +//====================================================================== diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v index 1324afb..56c7190 100644 --- a/rtl/src/verilog/eim_indicator.v +++ b/rtl/src/verilog/eim_indicator.v @@ -1,36 +1,76 @@ -`timescale 1ns / 1ps - -module eim_indicator - ( - sys_clk, sys_rst, - eim_active, - led_out - ); - - // - // Ports - // - input wire sys_clk; - input wire sys_rst; - input wire eim_active; - output wire led_out; - - // - // Parameters - // - localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. - - // - // Counter - // - reg [CNT_BITS-1:0] cnt; - - always @(posedge sys_clk) - // - if (sys_rst) cnt <= {CNT_BITS{1'b0}}; - else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; - else if (eim_active) cnt <= {CNT_BITS{1'b1}}; - - assign led_out = ~cnt[CNT_BITS-1]; - -endmodule +//====================================================================== +// +// eim_indicator.v +// --------------- +// A simple LED indicator to show that the EIM is alive. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module eim_indicator + ( + sys_clk, sys_rst, + eim_active, + led_out + ); + + // + // Ports + // + input wire sys_clk; + input wire sys_rst; + input wire eim_active; + output wire led_out; + + // + // Parameters + // + localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. + + // + // Counter + // + reg [CNT_BITS-1:0] cnt; + + always @(posedge sys_clk) + // + if (sys_rst) cnt <= {CNT_BITS{1'b0}}; + else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; + else if (eim_active) cnt <= {CNT_BITS{1'b1}}; + + assign led_out = ~cnt[CNT_BITS-1]; + +endmodule + +//====================================================================== +// EOF eim_indicator.v +//====================================================================== diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 57ef434..890b8bc 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -1,4 +1,42 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// novena_baseline_top.v +// --------------------- +// Top module for the Cryptech Novena FPGA framework. This design +// allow us to run the EIM interface at one clock and cores including +// core selector with the always present global clock. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module novena_baseline_top ( @@ -130,3 +168,7 @@ module novena_baseline_top endmodule + +//====================================================================== +// EOF novena_baseline_top.v +//====================================================================== diff --git a/rtl/src/verilog/novena_clkmgr.v b/rtl/src/verilog/novena_clkmgr.v index 5713383..c68cb43 100644 --- a/rtl/src/verilog/novena_clkmgr.v +++ b/rtl/src/verilog/novena_clkmgr.v @@ -1,4 +1,41 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// novena_clkmgr.v +// --------------- +// Clock and reset implementation for the Cryptech Novena +// FPGA framework. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module novena_clkmgr ( @@ -98,3 +135,7 @@ module novena_clkmgr endmodule + +//====================================================================== +// EOF novena_clkmgr.v +//====================================================================== -- cgit v1.2.3