From 5f769e9b78a61d6b69355a6aae8572128a8f54a3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 15:06:55 -0500 Subject: Reformat verilog code for readability. --- rtl/src/verilog/novena_clkmgr.v | 142 ++++++++++++++++++++-------------------- 1 file changed, 72 insertions(+), 70 deletions(-) (limited to 'rtl/src/verilog/novena_clkmgr.v') diff --git a/rtl/src/verilog/novena_clkmgr.v b/rtl/src/verilog/novena_clkmgr.v index c68cb43..00b2e5b 100644 --- a/rtl/src/verilog/novena_clkmgr.v +++ b/rtl/src/verilog/novena_clkmgr.v @@ -7,7 +7,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -38,100 +38,102 @@ //====================================================================== module novena_clkmgr - ( - gclk_p, gclk_n, - reset_mcu_b, - sys_clk, sys_rst, - bclk_in, bclk_out - ); + ( + input wire gclk_p, // signal from clock pins + input wire gclk_n, // - // - // Ports - // - input wire gclk_p; // signal from clock pins - input wire gclk_n; // + input wire reset_mcu_b, // cpu reset (async) - input wire reset_mcu_b; // cpu reset (async) + output wire sys_clk, // buffered system clock output + output wire sys_rst, // system reset output (sync) - output wire sys_clk; // buffered system clock output - output wire sys_rst; // system reset output (sync) + input wire bclk_in, // signal from clock pin + output wire bclk_out // buffered clock output + ); - input wire bclk_in; // signal from clock pin - output wire bclk_out; // buffered clock output + // + // Ports + // - // - // IBUFGDS - // - (* BUFFER_TYPE="NONE" *) - wire gclk; + // + // IBUFGDS + // + (* BUFFER_TYPE="NONE" *) + wire gclk; - IBUFGDS IBUFGDS_gclk - ( - .I (gclk_p), - .IB (gclk_n), - .O (gclk) - ); + IBUFGDS IBUFGDS_gclk + ( + .I(gclk_p), + .IB(gclk_n), + .O(gclk) + ); - // - // DCM - // - wire dcm_reset; // dcm reset - wire dcm_locked; // output clock valid - wire gclk_missing; // no input clock + // + // DCM + // + wire dcm_reset; // dcm reset + wire dcm_locked; // output clock valid + wire gclk_missing; // no input clock - clkmgr_dcm dcm - ( - .CLK_IN1 (gclk), - .RESET (dcm_reset), - .INPUT_CLK_STOPPED (gclk_missing), + clkmgr_dcm dcm + ( + .CLK_IN1(gclk), + .RESET(dcm_reset), + .INPUT_CLK_STOPPED(gclk_missing), - .CLK_OUT1 (sys_clk), - .CLK_VALID (dcm_locked) - ); + .CLK_OUT1(sys_clk), + .CLK_VALID(dcm_locked) + ); - // - // DCM Reset Logic - // + // + // DCM Reset Logic + // - /* DCM should be reset on power-up, when input clock is stopped or when the CPU gets reset. */ + /* DCM should be reset on power-up, when input clock is stopped or when the + * CPU gets reset. + */ - reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register - always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing) - // - if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) dcm_rst_shreg <= {16{1'b1}}; - else dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0}; + always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing) + // + if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) + dcm_rst_shreg <= {16{1'b1}}; + else + dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0}; - assign dcm_reset = dcm_rst_shreg[15]; + assign dcm_reset = dcm_rst_shreg[15]; - // - // System Reset Logic - // + // + // System Reset Logic + // - /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ + /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ - reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register - always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) - // - if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) sys_rst_shreg <= {16{1'b1}}; - else if (dcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) + // + if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) + sys_rst_shreg <= {16{1'b1}}; + else if (dcm_locked == 1'b1) + sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; - assign sys_rst = sys_rst_shreg[15]; + assign sys_rst = sys_rst_shreg[15]; - // - // BCLK BUFG - // - BUFG BUFG_BCLK - ( - .I (bclk_in), - .O (bclk_out) - ); + // + // BCLK BUFG + // + BUFG BUFG_BCLK + ( + .I(bclk_in), + .O(bclk_out) + ); endmodule -- cgit v1.2.3