From 560ebacb0c576b92d7b64d728423683ad974885e Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 12:03:47 -0500 Subject: Updates from Pavel with new mux. 1. EIM arbiter was updated to take advantage of 3 additional address lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address lines instead of 16, that means 19-2=17 effective bits when using 32-bit access. 2. In the doc directory there's a draft version of current EIM memory map. 3. I've figured out why you guys could not use read and write signals from the arbiter the way they were supposed to be used. I was wrong when I expected Joachim's cores to have registered outputs. They have a combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so we have to register data coming out of cores. I've added these three lines to every core wrapper (sha1.v, sha256.v and sha512.v): reg [31 : 0] tmp_read_data_reg; always @(posedge clk) tmp_read_data_reg <= tmp_read_data; assign read_data = tmp_read_data_reg; 4. Joachim told me, that we are going to have different types of cores (HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have separate modules for every core type. RNG and CIPHER selectors right now are just templates with some dummy registers. Here is what was modified in the HASH multiplexor: 4a. Core number 0 was added. It is not an actual HASH core, but a set of global (board-level) registers. I've added three registers so far: board type, bitstream version and one writeable dummy general-purpose register. 4b. Core instantiation was made conditional to allow selecting of what cores to actually implement. We can have a project that offers a large number of cores, so people can disable unnecessary cores to speed up compile time and to save some slices for something else. 4c. I have disconnected .error() output from cores. As far as I understand it gets asserted when some non-existent register is being addressed. In most projects that I've seen writes to empty regions of memory are discarded and reads return zeroes. If you really need this kind of error checking, please re-connect this output as needed. 4d. core_selector.v has an instruction on how to add new HASH cores to our design. 5. TC11() was added to hash_tester.c to check that we can read global board-level registers and that we have access to segments other than HASH. The last check reads dummy registers from RNG and CIPHER segments (which are just templates now), this effectively tests the 3 new added address bits. --- rtl/src/verilog/novena_baseline_top.v | 40 ++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'rtl/src/verilog/novena_baseline_top.v') diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 20bf28d..cc9e5e7 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -49,13 +49,14 @@ module novena_baseline_top input wire reset_mcu_b_pin, // Cryptech avalanche noise board input and LED outputs - input wire ct_avalanche_noise, - output wire [07 : 0] ct_avalanche_led, + input wire ct_noise, + output wire [07 : 0] ct_led, // EIM interface input wire eim_bclk, // EIM burst clock. Started by the CPU. input wire eim_cs0_n, // Chip select (active low). - inout wire [15 : 0] eim_da, // Bidirectional address and data port. + inout wire [15 : 0] eim_da, // Bidirectional address and data port. + input wire [18: 16] eim_a, // MSB part of address port. input wire eim_lba_n, // Latch address signal (active low). input wire eim_wr_n, // write enable signal (active low). input wire eim_oe_n, // output enable signal (active low). @@ -98,7 +99,7 @@ module novena_baseline_top // EIM arbiter handles EIM access and transfers it into // `sys_clk' clock domain. //---------------------------------------------------------------- - wire [13: 0] sys_eim_addr; + wire [16: 0] sys_eim_addr; wire sys_eim_wr; wire sys_eim_rd; wire [31: 0] sys_eim_dout; @@ -107,9 +108,10 @@ module novena_baseline_top eim_arbiter eim ( .eim_bclk(eim_bclk_buf), - .eim_cs0_n (eim_cs0_n), - .eim_da(eim_da), - .eim_lba_n (eim_lba_n), + .eim_cs0_n(eim_cs0_n), + .eim_da(eim_da), + .eim_a(eim_a), + .eim_lba_n(eim_lba_n), .eim_wr_n(eim_wr_n), .eim_oe_n(eim_oe_n), .eim_wait_n(eim_wait_n), @@ -125,24 +127,23 @@ module novena_baseline_top //---------------------------------------------------------------- - // Core Selector (MUX) + // Memory Mapper // - // This multiplexer is used to map ore registers into - // EIM address space and select which core to send EIM read and - // write operations to. - //---------------------------------------------------------------- - core_selector mux - ( - .sys_clk(sys_clk), + // This multiplexer is used to map different types of cores, such as + // hashes, RNGs and ciphers to different regions (segments) of memory. + //---------------------------------------------------------------- + eim_memory mem + ( + .sys_clk(sys_clk), .sys_rst(sys_rst), .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), - .write_data(sys_eim_dout), - .read_data(sys_eim_din) - ); + .sys_write_data(sys_eim_dout), + .sys_read_data(sys_eim_din) + ); //---------------------------------------------------------------- @@ -166,7 +167,7 @@ module novena_baseline_top // Logic specific to the Cryptech use of the Novena. // Currently we just hard wire the LED outputs. //---------------------------------------------------------------- - assign ct_avalanche_led = 8'h55; + assign ct_led = {8{ct_noise}}; //---------------------------------------------------------------- @@ -178,6 +179,7 @@ module novena_baseline_top // been configured. //---------------------------------------------------------------- assign apoptosis_pin = 1'b0; + endmodule -- cgit v1.2.3 From 5f769e9b78a61d6b69355a6aae8572128a8f54a3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 15:06:55 -0500 Subject: Reformat verilog code for readability. --- rtl/src/verilog/novena_baseline_top.v | 284 +++++++++++++++++----------------- 1 file changed, 142 insertions(+), 142 deletions(-) (limited to 'rtl/src/verilog/novena_baseline_top.v') diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index cc9e5e7..3499fa3 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -8,7 +8,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -39,147 +39,147 @@ //====================================================================== module novena_baseline_top - ( - // Differential input for 50 MHz general clock. - input wire gclk_p_pin, - input wire gclk_n_pin, - - // Reset controlled by the CPU. - // this must be configured as input w/pullup - input wire reset_mcu_b_pin, - - // Cryptech avalanche noise board input and LED outputs - input wire ct_noise, - output wire [07 : 0] ct_led, - - // EIM interface - input wire eim_bclk, // EIM burst clock. Started by the CPU. - input wire eim_cs0_n, // Chip select (active low). - inout wire [15 : 0] eim_da, // Bidirectional address and data port. - input wire [18: 16] eim_a, // MSB part of address port. - input wire eim_lba_n, // Latch address signal (active low). - input wire eim_wr_n, // write enable signal (active low). - input wire eim_oe_n, // output enable signal (active low). - output wire eim_wait_n, // Data wait signal (active low). - - // Novena utility ports - apoptosis_pin, // Hold low to not restart after config. - led_pin // LED on edge close to the FPGA. - ); - - - //---------------------------------------------------------------- - // Clock Manager - // - // Clock manager is used to buffer BCLK, generate SYS_CLK - // from GCLK and implement the reset logic. - //---------------------------------------------------------------- - wire sys_clk; - wire sys_rst; - wire eim_bclk_buf; - - novena_clkmgr clkmgr - ( - .gclk_p(gclk_p_pin), - .gclk_n(gclk_n_pin), - - .reset_mcu_b(reset_mcu_b_pin), - - .sys_clk(sys_clk), - .sys_rst(sys_rst), - - .bclk_in(eim_bclk), - .bclk_out(eim_bclk_buf) - ); - - - //---------------------------------------------------------------- - // EIM Arbiter - // - // EIM arbiter handles EIM access and transfers it into - // `sys_clk' clock domain. - //---------------------------------------------------------------- - wire [16: 0] sys_eim_addr; - wire sys_eim_wr; - wire sys_eim_rd; - wire [31: 0] sys_eim_dout; - wire [31: 0] sys_eim_din; - - eim_arbiter eim - ( - .eim_bclk(eim_bclk_buf), - .eim_cs0_n(eim_cs0_n), - .eim_da(eim_da), - .eim_a(eim_a), - .eim_lba_n(eim_lba_n), - .eim_wr_n(eim_wr_n), - .eim_oe_n(eim_oe_n), - .eim_wait_n(eim_wait_n), - - .sys_clk(sys_clk), - - .sys_addr(sys_eim_addr), - .sys_wren(sys_eim_wr), - .sys_data_out(sys_eim_dout), - .sys_rden(sys_eim_rd), - .sys_data_in(sys_eim_din) - ); - - - //---------------------------------------------------------------- - // Memory Mapper - // - // This multiplexer is used to map different types of cores, such as - // hashes, RNGs and ciphers to different regions (segments) of memory. - //---------------------------------------------------------------- - eim_memory mem - ( - .sys_clk(sys_clk), - .sys_rst(sys_rst), - - .sys_eim_addr(sys_eim_addr), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - - .sys_write_data(sys_eim_dout), - .sys_read_data(sys_eim_din) - ); - - - //---------------------------------------------------------------- - // LED Driver - // - // A simple utility LED driver that turns on the Novena - // board LED when the EIM interface is active. - //---------------------------------------------------------------- - eim_indicator led - ( - .sys_clk(sys_clk), - .sys_rst(sys_rst), - .eim_active(sys_eim_wr | sys_eim_rd), - .led_out(led_pin) - ); - - - //---------------------------------------------------------------- - // Cryptech Logic - // - // Logic specific to the Cryptech use of the Novena. - // Currently we just hard wire the LED outputs. - //---------------------------------------------------------------- - assign ct_led = {8{ct_noise}}; - - - //---------------------------------------------------------------- - // Novena Patch - // - // Patch logic to keep the Novena board happy. - // The apoptosis_pin pin must be kept low or the whole board - // (more exactly the CPU) will be reset after the FPGA has - // been configured. - //---------------------------------------------------------------- - assign apoptosis_pin = 1'b0; - + ( + // Differential input for 50 MHz general clock. + input wire gclk_p_pin, + input wire gclk_n_pin, + + // Reset controlled by the CPU. + // this must be configured as input w/pullup + input wire reset_mcu_b_pin, + + // Cryptech avalanche noise board input and LED outputs + input wire ct_noise, + output wire [7 : 0] ct_led, + + // EIM interface + input wire eim_bclk, // EIM burst clock. Started by the CPU. + input wire eim_cs0_n, // Chip select (active low). + inout wire [15 : 0] eim_da, // Bidirectional address and data port. + input wire [18: 16] eim_a, // MSB part of address port. + input wire eim_lba_n, // Latch address signal (active low). + input wire eim_wr_n, // write enable signal (active low). + input wire eim_oe_n, // output enable signal (active low). + output wire eim_wait_n, // Data wait signal (active low). + + // Novena utility ports + apoptosis_pin, // Hold low to not restart after config. + led_pin // LED on edge close to the FPGA. + ); + + + //---------------------------------------------------------------- + // Clock Manager + // + // Clock manager is used to buffer BCLK, generate SYS_CLK + // from GCLK and implement the reset logic. + //---------------------------------------------------------------- + wire sys_clk; + wire sys_rst; + wire eim_bclk_buf; + + novena_clkmgr clkmgr + ( + .gclk_p(gclk_p_pin), + .gclk_n(gclk_n_pin), + + .reset_mcu_b(reset_mcu_b_pin), + + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .bclk_in(eim_bclk), + .bclk_out(eim_bclk_buf) + ); + + + //---------------------------------------------------------------- + // EIM Arbiter + // + // EIM arbiter handles EIM access and transfers it into + // `sys_clk' clock domain. + //---------------------------------------------------------------- + wire [16: 0] sys_eim_addr; + wire sys_eim_wr; + wire sys_eim_rd; + wire [31: 0] sys_eim_dout; + wire [31: 0] sys_eim_din; + + eim_arbiter eim + ( + .eim_bclk(eim_bclk_buf), + .eim_cs0_n(eim_cs0_n), + .eim_da(eim_da), + .eim_a(eim_a), + .eim_lba_n(eim_lba_n), + .eim_wr_n(eim_wr_n), + .eim_oe_n(eim_oe_n), + .eim_wait_n(eim_wait_n), + + .sys_clk(sys_clk), + + .sys_addr(sys_eim_addr), + .sys_wren(sys_eim_wr), + .sys_data_out(sys_eim_dout), + .sys_rden(sys_eim_rd), + .sys_data_in(sys_eim_din) + ); + + + //---------------------------------------------------------------- + // Memory Mapper + // + // This multiplexer is used to map different types of cores, such as + // hashes, RNGs and ciphers to different regions (segments) of memory. + //---------------------------------------------------------------- + eim_memory mem + ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .sys_eim_addr(sys_eim_addr), + .sys_eim_wr(sys_eim_wr), + .sys_eim_rd(sys_eim_rd), + + .sys_write_data(sys_eim_dout), + .sys_read_data(sys_eim_din) + ); + + + //---------------------------------------------------------------- + // LED Driver + // + // A simple utility LED driver that turns on the Novena + // board LED when the EIM interface is active. + //---------------------------------------------------------------- + eim_indicator led + ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + .eim_active(sys_eim_wr | sys_eim_rd), + .led_out(led_pin) + ); + + + //---------------------------------------------------------------- + // Cryptech Logic + // + // Logic specific to the Cryptech use of the Novena. + // Currently we just hard wire the LED outputs. + //---------------------------------------------------------------- + assign ct_led = {8{ct_noise}}; + + + //---------------------------------------------------------------- + // Novena Patch + // + // Patch logic to keep the Novena board happy. + // The apoptosis_pin pin must be kept low or the whole board + // (more exactly the CPU) will be reset after the FPGA has + // been configured. + //---------------------------------------------------------------- + assign apoptosis_pin = 1'b0; + endmodule -- cgit v1.2.3