From 5f769e9b78a61d6b69355a6aae8572128a8f54a3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 15:06:55 -0500 Subject: Reformat verilog code for readability. --- rtl/src/verilog/eim_indicator.v | 49 ++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 28 deletions(-) (limited to 'rtl/src/verilog/eim_indicator.v') diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v index 56c7190..cf9751d 100644 --- a/rtl/src/verilog/eim_indicator.v +++ b/rtl/src/verilog/eim_indicator.v @@ -6,7 +6,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -37,37 +37,30 @@ //====================================================================== module eim_indicator - ( - sys_clk, sys_rst, - eim_active, - led_out - ); + ( + input wire sys_clk, + input wire sys_rst, + input wire eim_active, + output wire led_out + ); - // - // Ports - // - input wire sys_clk; - input wire sys_rst; - input wire eim_active; - output wire led_out; + // + // Parameters + // + localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. - // - // Parameters - // - localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz. + // + // Counter + // + reg [CNT_BITS-1:0] cnt; - // - // Counter - // - reg [CNT_BITS-1:0] cnt; + always @(posedge sys_clk) + // + if (sys_rst) cnt <= {CNT_BITS{1'b0}}; + else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; + else if (eim_active) cnt <= {CNT_BITS{1'b1}}; - always @(posedge sys_clk) - // - if (sys_rst) cnt <= {CNT_BITS{1'b0}}; - else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1; - else if (eim_active) cnt <= {CNT_BITS{1'b1}}; - - assign led_out = ~cnt[CNT_BITS-1]; + assign led_out = ~cnt[CNT_BITS-1]; endmodule -- cgit v1.2.3