From 86311d72381423582f2de5f91fa9fbb447098934 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 2 Feb 2015 16:45:38 +0100 Subject: Changed core_selector to instead use the cryptech sha256 core. --- rtl/src/verilog/core_selector.v | 95 +++++------------------------------------ 1 file changed, 10 insertions(+), 85 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 8ce2003..7f92e43 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,94 +48,19 @@ module core_selector input wire [31 : 0] write_data ); - // - // Internal Registers - // - reg [31: 0] reg_x = {32{1'b0}}; - reg [31: 0] reg_y = {32{1'b0}}; - reg [15: 0] reg_ctl = {16{1'b0}}; - reg [31: 0] read_data_reg = {32{1'b0}}; + sha256 sha256_inst( + .clk(sys_clk), + .reset_n(~sys_rst), - // - // Parameters - // - localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address - localparam ADDER_OFFSET_REG_X = 2'd0; // X - localparam ADDER_OFFSET_REG_Y = 2'd1; // Y - localparam ADDER_OFFSET_REG_Z = 2'd2; // Z - localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL} - - - /* This flag detects whether adder core is being addressed. */ - wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; - - /* These flags detect whether write or read access is requested. */ - wire eim_access_write = sys_eim_wr & eim_access_adder; - wire eim_access_read = sys_eim_rd & eim_access_adder; - - - // - // Write Request Handler - // - always @(posedge sys_clk) - // - if (sys_rst) begin - reg_x <= {32{1'b0}}; - reg_y <= {32{1'b0}}; - reg_ctl <= {16{1'b0}}; - end else if (eim_access_write) begin - // - case (sys_eim_addr[1:0]) - ADDER_OFFSET_REG_X: reg_x <= write_data; - ADDER_OFFSET_REG_Y: reg_y <= write_data; - ADDER_OFFSET_REG_SC: reg_ctl <= write_data[15 : 0]; - endcase - // - end - - - // - // Read Request Handler - // - wire [31: 0] reg_z; - wire [15: 0] reg_sts; - - always @(posedge sys_clk) - // - if (sys_rst) read_data_reg <= {32{1'b0}}; - // - else if (eim_access_read) begin - // - case (sys_eim_addr[1:0]) - ADDER_OFFSET_REG_X: read_data_reg <= reg_x; - ADDER_OFFSET_REG_Y: read_data_reg <= reg_y; - ADDER_OFFSET_REG_Z: read_data_reg <= reg_z; - ADDER_OFFSET_REG_SC: read_data_reg <= {reg_sts, reg_ctl}; - endcase - // - end - - assign read_data = read_data_reg; - - - // - // Demo Adder Core - // - demo_adder adder_core - ( - .clk (sys_clk), - .rst (sys_rst), - - .x (reg_x), - .y (reg_y), - .z (reg_z), - - .ctl (reg_ctl), - .sts (reg_sts) - ); - + .cs(sys_eim_rd | sys_eim_wr), + .we(sys_eim_wr), + .address(sys_eim_addr[7 : 0]), + .write_data(write_data), + .read_data(read_data), + .error() + ); endmodule -- cgit v1.2.3 From f1fe0708e988356413f3160c6a85dc8d82eba3a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 2 Feb 2015 20:54:59 +0100 Subject: Added real prefix detection of sha255 core. --- rtl/src/verilog/core_selector.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 7f92e43..092b8ca 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,12 +48,15 @@ module core_selector input wire [31 : 0] write_data ); + parameter SHA256_BASE = 6'h14; + wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); + wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); sha256 sha256_inst( .clk(sys_clk), .reset_n(~sys_rst), - .cs(sys_eim_rd | sys_eim_wr), + .cs(sha256_cs), .we(sys_eim_wr), .address(sys_eim_addr[7 : 0]), -- cgit v1.2.3 From eff75209176003629d3840809fc220a458fd89f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Mon, 2 Feb 2015 21:06:21 +0100 Subject: Passes build without any warnings. --- rtl/src/verilog/core_selector.v | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 092b8ca..4d3a218 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,16 +48,22 @@ module core_selector input wire [31 : 0] write_data ); - parameter SHA256_BASE = 6'h14; - wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); - wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); +// parameter SHA256_BASE = 6'h14; +// wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); +// wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); + + localparam SHA256_BASE_ADDR = 6'h14; + wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; + wire read_access = sys_eim_wr & access_sha256; + wire write_access = sys_eim_rd & access_sha256; + wire select = read_access | write_access; sha256 sha256_inst( .clk(sys_clk), .reset_n(~sys_rst), - .cs(sha256_cs), - .we(sys_eim_wr), + .cs(select), + .we(write_access), .address(sys_eim_addr[7 : 0]), .write_data(write_data), -- cgit v1.2.3 From 8bcab15be72dc172cbb06c05407f6778ea3190ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 3 Feb 2015 05:18:36 +0100 Subject: More attempts at getting the addresss decoder to work... --- rtl/src/verilog/core_selector.v | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 4d3a218..a18bfe6 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,28 +48,26 @@ module core_selector input wire [31 : 0] write_data ); -// parameter SHA256_BASE = 6'h14; -// wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); -// wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); - localparam SHA256_BASE_ADDR = 6'h14; wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; - wire read_access = sys_eim_wr & access_sha256; - wire write_access = sys_eim_rd & access_sha256; + wire read_access = sys_eim_rd & access_sha256; + wire write_access = sys_eim_wr & access_sha256; wire select = read_access | write_access; - sha256 sha256_inst( - .clk(sys_clk), - .reset_n(~sys_rst), - - .cs(select), - .we(write_access), + assign read_data = (sys_eim_rd) ? 32'hdeadbeef : 32'haa55aa55; - .address(sys_eim_addr[7 : 0]), - .write_data(write_data), - .read_data(read_data), - .error() - ); +// sha256 sha256_inst( +// .clk(sys_clk), +// .reset_n(~sys_rst), +// +// .cs(select), +// .we(write_access), +// +// .address(sys_eim_addr[7 : 0]), +// .write_data(write_data), +// .read_data(read_data), +// .error() +// ); endmodule -- cgit v1.2.3 From f0ded923cc20dbc39336f3f2e8f083033dba6f9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 3 Feb 2015 21:45:24 +0100 Subject: (1) Updated core selector with logic to connect sha256. (2) Adding test sw that is able to talk to the sha256 core and perform a hash operation. --- rtl/src/verilog/core_selector.v | 106 ++++++++++++++++++++++++++++++++++------ 1 file changed, 90 insertions(+), 16 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index a18bfe6..3f74a26 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,26 +48,100 @@ module core_selector input wire [31 : 0] write_data ); - localparam SHA256_BASE_ADDR = 6'h14; - wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; - wire read_access = sys_eim_rd & access_sha256; - wire write_access = sys_eim_wr & access_sha256; - wire select = read_access | write_access; - assign read_data = (sys_eim_rd) ? 32'hdeadbeef : 32'haa55aa55; + // + // Parameters + // + localparam ADDER_BASE_ADDR = 6'h00; // upper 6 bits of address + localparam ADDER_OFFSET_X_REG = 8'h00; // X + localparam ADDER_OFFSET_Y_REG = 8'h01; // Y -// sha256 sha256_inst( -// .clk(sys_clk), -// .reset_n(~sys_rst), + + /* This flag detects whether adder core is being addressed. */ + wire eim_access_adder = (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; + + /* These flags detect whether write or read access is requested. */ + wire eim_access_write = sys_eim_wr & eim_access_adder; + wire eim_access_read = sys_eim_rd & eim_access_adder; + wire select = eim_access_read | eim_access_write; + +// reg [31 : 0] read_data_reg; +// reg [31 : 0] y_reg; +// reg [31 : 0] x_reg; +// +// // +// // Write Request Handler +// // +// always @(posedge sys_clk) +// // +// if (sys_rst) begin +// x_reg <= 32'hdeaddead; +// y_reg <= 32'hbeefbeef; +// end +// else if (eim_access_write) begin +// case (sys_eim_addr[7:0]) +// ADDER_OFFSET_X_REG: x_reg <= write_data; +// ADDER_OFFSET_Y_REG: y_reg <= write_data; +// endcase +// end +// +// +// // +// // Read Request Handler +// always @(posedge sys_clk) +// // +// if (sys_rst) +// read_data_reg <= 32'h00000000; +// // +// else if (eim_access_read) begin +// // +// case (sys_eim_addr[7:0]) +// ADDER_OFFSET_X_REG: read_data_reg <= x_reg; +// ADDER_OFFSET_Y_REG: read_data_reg <= y_reg; +// endcase +// // +// end + +// assign read_data = read_data_reg; + + + // localparam SHA256_BASE_ADDR = 6'h14; + // + // wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; + // wire read_access = sys_eim_rd & access_sha256; + // wire write_access = sys_eim_wr & access_sha256; + // wire select = read_access | write_access; + +// reg [31 : 0] read_data_reg; +// wire [31 : 0] sha_read_data; // -// .cs(select), -// .we(write_access), +// assign read_data = read_data_reg; // -// .address(sys_eim_addr[7 : 0]), -// .write_data(write_data), -// .read_data(read_data), -// .error() -// ); +// always @ (posedge sys_clk) +// begin +// if (sys_rst) +// begin +// read_data_reg <= 32'h00000000; +// end +// else +// begin +// read_data_reg <= sha_read_data; +// end +// end + + + sha256 sha256_inst( + .clk(sys_clk), + .reset_n(1'b1), + + .cs(eim_access_adder), + .we(sys_eim_wr), + + .address(sys_eim_addr[7 : 0]), + .write_data(write_data), + .read_data(read_data), + .error() + ); endmodule -- cgit v1.2.3 From 13b8166c8989b5e83b0c998279c60c17bf46e890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 5 Feb 2015 15:31:33 -0500 Subject: add all SHA cores (hello coretest_hashes) --- rtl/src/verilog/core_selector.v | 296 +++++++++++++++++++++++++--------------- 1 file changed, 186 insertions(+), 110 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 3f74a26..7479848 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,18 +1,21 @@ //====================================================================== // -// core_selector.v -// --------------- -// Core selector Cryptech Novena FPGA framework. +// coretest_hashes.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. // // -// Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. -// +// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. +// // Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the @@ -37,111 +40,184 @@ //====================================================================== module core_selector - ( - input wire sys_clk, + ( + input wire sys_clk, input wire sys_rst, - input wire [13: 0] sys_eim_addr, + input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, output wire [31 : 0] read_data, - input wire [31 : 0] write_data - ); - - - // - // Parameters - // - localparam ADDER_BASE_ADDR = 6'h00; // upper 6 bits of address - localparam ADDER_OFFSET_X_REG = 8'h00; // X - localparam ADDER_OFFSET_Y_REG = 8'h01; // Y - - - /* This flag detects whether adder core is being addressed. */ - wire eim_access_adder = (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; - - /* These flags detect whether write or read access is requested. */ - wire eim_access_write = sys_eim_wr & eim_access_adder; - wire eim_access_read = sys_eim_rd & eim_access_adder; - wire select = eim_access_read | eim_access_write; - -// reg [31 : 0] read_data_reg; -// reg [31 : 0] y_reg; -// reg [31 : 0] x_reg; -// -// // -// // Write Request Handler -// // -// always @(posedge sys_clk) -// // -// if (sys_rst) begin -// x_reg <= 32'hdeaddead; -// y_reg <= 32'hbeefbeef; -// end -// else if (eim_access_write) begin -// case (sys_eim_addr[7:0]) -// ADDER_OFFSET_X_REG: x_reg <= write_data; -// ADDER_OFFSET_Y_REG: y_reg <= write_data; -// endcase -// end -// -// -// // -// // Read Request Handler -// always @(posedge sys_clk) -// // -// if (sys_rst) -// read_data_reg <= 32'h00000000; -// // -// else if (eim_access_read) begin -// // -// case (sys_eim_addr[7:0]) -// ADDER_OFFSET_X_REG: read_data_reg <= x_reg; -// ADDER_OFFSET_Y_REG: read_data_reg <= y_reg; -// endcase -// // -// end - -// assign read_data = read_data_reg; - - - // localparam SHA256_BASE_ADDR = 6'h14; - // - // wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; - // wire read_access = sys_eim_rd & access_sha256; - // wire write_access = sys_eim_wr & access_sha256; - // wire select = read_access | write_access; - -// reg [31 : 0] read_data_reg; -// wire [31 : 0] sha_read_data; -// -// assign read_data = read_data_reg; -// -// always @ (posedge sys_clk) -// begin -// if (sys_rst) -// begin -// read_data_reg <= 32'h00000000; -// end -// else -// begin -// read_data_reg <= sha_read_data; -// end -// end - - - sha256 sha256_inst( - .clk(sys_clk), - .reset_n(1'b1), - - .cs(eim_access_adder), - .we(sys_eim_wr), - - .address(sys_eim_addr[7 : 0]), - .write_data(write_data), - .read_data(read_data), - .error() - ); + input wire [31 : 0] write_data + ); + + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter SHA1_ADDR_PREFIX = 6'b000100; // 0x1000 - 0x13ff + parameter SHA256_ADDR_PREFIX = 6'b001000; // 0x2000 - 0x23ff + parameter SHA512_ADDR_PREFIX = 6'b001100; // 0x3000 - 0x33ff + + + //---------------------------------------------------------------- + // Wires and registers + //---------------------------------------------------------------- + wire clk = sys_clk; + wire reset_n = !sys_rst; + wire [13:0] address = sys_eim_addr; + wire cs = sys_eim_wr | sys_eim_rd; + wire we = sys_eim_wr; + + reg [31:0] read_reg; + reg error_reg; + + // sha1 connections. + reg sha1_cs; + reg sha1_we; + reg [7:0] sha1_address; + reg [31:0] sha1_write_data; + wire [31:0] sha1_read_data; + wire sha1_error; + + // sha256 connections. + reg sha256_cs; + reg sha256_we; + reg [7:0] sha256_address; + reg [31:0] sha256_write_data; + wire [31:0] sha256_read_data; + wire sha256_error; + + // sha512 connections. + reg sha512_cs; + reg sha512_we; + reg [7:0] sha512_address; + reg [31:0] sha512_write_data; + wire [31:0] sha512_read_data; + wire sha512_error; + + + //---------------------------------------------------------------- + // Concurrent assignment. + //---------------------------------------------------------------- + assign read_data = read_reg; + + //---------------------------------------------------------------- + // Core instantiations. + //---------------------------------------------------------------- + sha1 sha1( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha1_cs), + .we(sha1_we), + + // Data ports. + .address(sha1_address), + .write_data(sha1_write_data), + .read_data(sha1_read_data), + .error(sha1_error) + ); + + + sha256 sha256( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha256_cs), + .we(sha256_we), + + // Data ports. + .address(sha256_address), + .write_data(sha256_write_data), + .read_data(sha256_read_data), + .error(sha256_error) + ); + + + sha512 sha512( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha512_cs), + .we(sha512_we), + + // Data ports. + .address(sha512_address), + .write_data(sha512_write_data), + .read_data(sha512_read_data), + .error(sha512_error) + ); + + //---------------------------------------------------------------- + // address_mux + // + // Combinational data mux that handles addressing between + // cores using the 32-bit memory like interface. + //---------------------------------------------------------------- + always @* + begin : address_mux + // Default assignments. + sha1_cs = 0; + sha1_we = 0; + sha1_address = 8'h00; + sha1_write_data = 32'h00000000; + + sha256_cs = 0; + sha256_we = 0; + sha256_address = 8'h00; + sha256_write_data = 32'h00000000; + + sha512_cs = 0; + sha512_we = 0; + sha512_address = 8'h00; + sha512_write_data = 32'h00000000; + + // address mux + case (address[13:8]) + SHA1_ADDR_PREFIX: + begin + sha1_cs = 1; + sha1_we = we; + sha1_address = address[7:0]; + sha1_write_data = write_data; + read_reg = sha1_read_data; + error_reg = sha1_error; + end + + SHA256_ADDR_PREFIX: + begin + sha256_cs = 1; + sha256_we = we; + sha256_address = address[7:0]; + sha256_write_data = write_data; + read_reg = sha256_read_data; + error_reg = sha256_error; + end + + SHA512_ADDR_PREFIX: + begin + sha512_cs = 1; + sha512_we = we; + sha512_address = address[7:0]; + sha512_write_data = write_data; + read_reg = sha512_read_data; + error_reg = sha512_error; + end + + default: + begin + read_reg = 32'hZZZZ; + end + endcase + + end // address_mux endmodule -- cgit v1.2.3 From 560ebacb0c576b92d7b64d728423683ad974885e Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 12:03:47 -0500 Subject: Updates from Pavel with new mux. 1. EIM arbiter was updated to take advantage of 3 additional address lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address lines instead of 16, that means 19-2=17 effective bits when using 32-bit access. 2. In the doc directory there's a draft version of current EIM memory map. 3. I've figured out why you guys could not use read and write signals from the arbiter the way they were supposed to be used. I was wrong when I expected Joachim's cores to have registered outputs. They have a combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so we have to register data coming out of cores. I've added these three lines to every core wrapper (sha1.v, sha256.v and sha512.v): reg [31 : 0] tmp_read_data_reg; always @(posedge clk) tmp_read_data_reg <= tmp_read_data; assign read_data = tmp_read_data_reg; 4. Joachim told me, that we are going to have different types of cores (HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have separate modules for every core type. RNG and CIPHER selectors right now are just templates with some dummy registers. Here is what was modified in the HASH multiplexor: 4a. Core number 0 was added. It is not an actual HASH core, but a set of global (board-level) registers. I've added three registers so far: board type, bitstream version and one writeable dummy general-purpose register. 4b. Core instantiation was made conditional to allow selecting of what cores to actually implement. We can have a project that offers a large number of cores, so people can disable unnecessary cores to speed up compile time and to save some slices for something else. 4c. I have disconnected .error() output from cores. As far as I understand it gets asserted when some non-existent register is being addressed. In most projects that I've seen writes to empty regions of memory are discarded and reads return zeroes. If you really need this kind of error checking, please re-connect this output as needed. 4d. core_selector.v has an instruction on how to add new HASH cores to our design. 5. TC11() was added to hash_tester.c to check that we can read global board-level registers and that we have access to segments other than HASH. The last check reads dummy registers from RNG and CIPHER segments (which are just templates now), this effectively tests the 3 new added address bits. --- rtl/src/verilog/core_selector.v | 365 +++++++++++++++++++++------------------- 1 file changed, 193 insertions(+), 172 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 7479848..e39a8b1 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,6 +1,6 @@ //====================================================================== // -// coretest_hashes.v +// core_selector.v // ----------------- // Top level wrapper that creates the Cryptech coretest system. // The wrapper contains instances of external interface, coretest @@ -42,182 +42,203 @@ module core_selector ( input wire sys_clk, - input wire sys_rst, + input wire sys_rst, + input wire sys_ena, input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, - output wire [31 : 0] read_data, - input wire [31 : 0] write_data + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data ); - - - //---------------------------------------------------------------- - // Internal constant and parameter definitions. - //---------------------------------------------------------------- - parameter SHA1_ADDR_PREFIX = 6'b000100; // 0x1000 - 0x13ff - parameter SHA256_ADDR_PREFIX = 6'b001000; // 0x2000 - 0x23ff - parameter SHA512_ADDR_PREFIX = 6'b001100; // 0x3000 - 0x33ff - - - //---------------------------------------------------------------- - // Wires and registers - //---------------------------------------------------------------- - wire clk = sys_clk; - wire reset_n = !sys_rst; - wire [13:0] address = sys_eim_addr; - wire cs = sys_eim_wr | sys_eim_rd; - wire we = sys_eim_wr; - - reg [31:0] read_reg; - reg error_reg; - - // sha1 connections. - reg sha1_cs; - reg sha1_we; - reg [7:0] sha1_address; - reg [31:0] sha1_write_data; - wire [31:0] sha1_read_data; - wire sha1_error; - - // sha256 connections. - reg sha256_cs; - reg sha256_we; - reg [7:0] sha256_address; - reg [31:0] sha256_write_data; - wire [31:0] sha256_read_data; - wire sha256_error; - - // sha512 connections. - reg sha512_cs; - reg sha512_we; - reg [7:0] sha512_address; - reg [31:0] sha512_write_data; - wire [31:0] sha512_read_data; - wire sha512_error; - - - //---------------------------------------------------------------- - // Concurrent assignment. - //---------------------------------------------------------------- - assign read_data = read_reg; - - //---------------------------------------------------------------- - // Core instantiations. - //---------------------------------------------------------------- - sha1 sha1( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha1_cs), - .we(sha1_we), - - // Data ports. - .address(sha1_address), - .write_data(sha1_write_data), - .read_data(sha1_read_data), - .error(sha1_error) - ); - - - sha256 sha256( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha256_cs), - .we(sha256_we), - - // Data ports. - .address(sha256_address), - .write_data(sha256_write_data), - .read_data(sha256_read_data), - .error(sha256_error) - ); - - - sha512 sha512( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha512_cs), - .we(sha512_we), - - // Data ports. - .address(sha512_address), - .write_data(sha512_write_data), - .read_data(sha512_read_data), - .error(sha512_error) - ); - - //---------------------------------------------------------------- - // address_mux - // - // Combinational data mux that handles addressing between - // cores using the 32-bit memory like interface. - //---------------------------------------------------------------- - always @* - begin : address_mux - // Default assignments. - sha1_cs = 0; - sha1_we = 0; - sha1_address = 8'h00; - sha1_write_data = 32'h00000000; - - sha256_cs = 0; - sha256_we = 0; - sha256_address = 8'h00; - sha256_write_data = 32'h00000000; - - sha512_cs = 0; - sha512_we = 0; - sha512_address = 8'h00; - sha512_write_data = 32'h00000000; - - // address mux - case (address[13:8]) - SHA1_ADDR_PREFIX: - begin - sha1_cs = 1; - sha1_we = we; - sha1_address = address[7:0]; - sha1_write_data = write_data; - read_reg = sha1_read_data; - error_reg = sha1_error; - end - - SHA256_ADDR_PREFIX: - begin - sha256_cs = 1; - sha256_we = we; - sha256_address = address[7:0]; - sha256_write_data = write_data; - read_reg = sha256_read_data; - error_reg = sha256_error; - end - - SHA512_ADDR_PREFIX: - begin - sha512_cs = 1; - sha512_we = we; - sha512_address = address[7:0]; - sha512_write_data = write_data; - read_reg = sha512_read_data; - error_reg = sha512_error; - end - - default: - begin - read_reg = 32'hZZZZ; - end - endcase - - end // address_mux + + + /* In this memory segment (HASHES) we have 14 address bits. Every core has 8-bit internal address space, + * so we can have up to 2^(14-8) = 64 cores here. + * + * Core #0 is not an actual HASH core, but a set of board-level (global) registers, that can be used to + * get information about hardware (board type, bitstream version and so on). + * + * So far we have three cores: SHA-1, SHA-256 and SHA-512. + */ + + /********************************************************* + * To add new HASH core named XXX follow the steps below * + ********************************************************* + * + * 1. Add corresponding `define under "List of Available Cores", this will allow users to exclude your + * core from implementation to save some slices in case they don't need it. + * + * `define USE_CORE_XXX + * + * + * 2. Choose address of your new core and add corresponding line under "Core Address Table". Core addresses + * can be in the range from 1 to 63 inclusively. Core address 0 is reserved for a page of global registers + * and must not be used. + * + * localparam CORE_ADDR_XXX = 6'dN; + * + * + * 3. Add instantiation of your new core after all existing cores surrounded by conditional synthesis directives. + * You also need a 32-bit output (read data) bus for your core and an enable flag. Note that sys_rst in + * an active-high sync reset signal. + * + * `ifdef USE_CORE_XXX + * wire [31: 0] read_data_xxx; + * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX); + * xxx xxx_inst + * ( + * .clk(sys_clk), + * .reset_n(~sys_rst), + * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), + * .we(sys_eim_wr), + * .address(addr_core_reg), + * .write_data(sys_write_data), + * .read_data(read_data_xxx), + * .error() + * ); + * `endif + * + * + * 4. Add previously created data bus to "Output (Read Data) Multiplexor" in the end of this file. + * + * `ifdef USE_CORE_XXX CORE_ADDR_XXX: sys_read_data_mux = read_data_xxx; `endif + * + */ + + + //---------------------------------------------------------------- + // Address Decoder + //---------------------------------------------------------------- + wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed + wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core + + + /* We can comment following lines to exclude cores from implementation + * in case we run out of slices. + */ + + //---------------------------------------------------------------- + // List of Available Cores + //---------------------------------------------------------------- + `define USE_CORE_SHA1 + `define USE_CORE_SHA256 + `define USE_CORE_SHA512 + + + //---------------------------------------------------------------- + // Core Address Table + //---------------------------------------------------------------- + localparam CORE_ADDR_GLOBAL_REGS = 6'd0; + localparam CORE_ADDR_SHA1 = 6'd1; + localparam CORE_ADDR_SHA256 = 6'd2; + localparam CORE_ADDR_SHA512 = 6'd3; + + + //---------------------------------------------------------------- + // Global Registers + //---------------------------------------------------------------- + wire [31: 0] read_data_global; + wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS); + novena_regs novena_regs_inst + ( + .clk(sys_clk), + .rst(sys_rst), + + .cs(enable_global & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_global) + ); + + + //---------------------------------------------------------------- + // SHA-1 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA1 + wire [31: 0] read_data_sha1; + wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1); + sha1 sha1_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha1), + .error() + ); + `endif + + + //---------------------------------------------------------------- + // SHA-256 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA256 + wire [31: 0] read_data_sha256; + wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256); + sha256 sha256_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha256), + .error() + ); + `endif + + + //---------------------------------------------------------------- + // SHA-512 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA512 + wire [31: 0] read_data_sha512; + wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512); + sha512 sha512_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha512), + .error() + ); + `endif + + + //---------------------------------------------------------------- + // Output (Read Data) Multiplexor + //---------------------------------------------------------------- + reg [31: 0] sys_read_data_mux; + assign sys_read_data = sys_read_data_mux; + + always @* + // + case (addr_core_num) + // + CORE_ADDR_GLOBAL_REGS: sys_read_data_mux = read_data_global; + `ifdef USE_CORE_SHA1 CORE_ADDR_SHA1: sys_read_data_mux = read_data_sha1; `endif + `ifdef USE_CORE_SHA256 CORE_ADDR_SHA256: sys_read_data_mux = read_data_sha256; `endif + `ifdef USE_CORE_SHA512 CORE_ADDR_SHA512: sys_read_data_mux = read_data_sha512; `endif + // + default: sys_read_data_mux = {32{1'b0}}; + // + endcase + endmodule -- cgit v1.2.3 From 0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 13:51:40 -0500 Subject: First stage of integration cleanup. Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory. --- rtl/src/verilog/core_selector.v | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index e39a8b1..8ac8909 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,7 +1,7 @@ //====================================================================== // // core_selector.v -// ----------------- +// --------------- // Top level wrapper that creates the Cryptech coretest system. // The wrapper contains instances of external interface, coretest // and the core to be tested. And if more than one core is @@ -170,8 +170,7 @@ module core_selector .address(addr_core_reg), .write_data(sys_write_data), - .read_data(read_data_sha1), - .error() + .read_data(read_data_sha1) ); `endif @@ -192,8 +191,7 @@ module core_selector .address(addr_core_reg), .write_data(sys_write_data), - .read_data(read_data_sha256), - .error() + .read_data(read_data_sha256) ); `endif @@ -214,8 +212,7 @@ module core_selector .address(addr_core_reg), .write_data(sys_write_data), - .read_data(read_data_sha512), - .error() + .read_data(read_data_sha512) ); `endif -- cgit v1.2.3 From 5f769e9b78a61d6b69355a6aae8572128a8f54a3 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 15:06:55 -0500 Subject: Reformat verilog code for readability. --- rtl/src/verilog/core_selector.v | 388 +++++++++++++++++++++------------------- 1 file changed, 203 insertions(+), 185 deletions(-) (limited to 'rtl/src/verilog/core_selector.v') diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 8ac8909..eef0a75 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -40,202 +40,220 @@ //====================================================================== module core_selector - ( - input wire sys_clk, - input wire sys_rst, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data - ); - - - /* In this memory segment (HASHES) we have 14 address bits. Every core has 8-bit internal address space, - * so we can have up to 2^(14-8) = 64 cores here. - * - * Core #0 is not an actual HASH core, but a set of board-level (global) registers, that can be used to - * get information about hardware (board type, bitstream version and so on). - * - * So far we have three cores: SHA-1, SHA-256 and SHA-512. - */ - - /********************************************************* - * To add new HASH core named XXX follow the steps below * - ********************************************************* - * - * 1. Add corresponding `define under "List of Available Cores", this will allow users to exclude your - * core from implementation to save some slices in case they don't need it. - * - * `define USE_CORE_XXX - * - * - * 2. Choose address of your new core and add corresponding line under "Core Address Table". Core addresses - * can be in the range from 1 to 63 inclusively. Core address 0 is reserved for a page of global registers - * and must not be used. - * - * localparam CORE_ADDR_XXX = 6'dN; - * - * - * 3. Add instantiation of your new core after all existing cores surrounded by conditional synthesis directives. - * You also need a 32-bit output (read data) bus for your core and an enable flag. Note that sys_rst in - * an active-high sync reset signal. - * - * `ifdef USE_CORE_XXX - * wire [31: 0] read_data_xxx; - * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX); - * xxx xxx_inst - * ( - * .clk(sys_clk), - * .reset_n(~sys_rst), - * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), - * .we(sys_eim_wr), - * .address(addr_core_reg), - * .write_data(sys_write_data), - * .read_data(read_data_xxx), - * .error() - * ); - * `endif - * - * - * 4. Add previously created data bus to "Output (Read Data) Multiplexor" in the end of this file. - * - * `ifdef USE_CORE_XXX CORE_ADDR_XXX: sys_read_data_mux = read_data_xxx; `endif - * - */ - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core - - - /* We can comment following lines to exclude cores from implementation - * in case we run out of slices. - */ - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - `define USE_CORE_SHA1 - `define USE_CORE_SHA256 - `define USE_CORE_SHA512 - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_GLOBAL_REGS = 6'd0; - localparam CORE_ADDR_SHA1 = 6'd1; - localparam CORE_ADDR_SHA256 = 6'd2; - localparam CORE_ADDR_SHA512 = 6'd3; - - - //---------------------------------------------------------------- - // Global Registers - //---------------------------------------------------------------- - wire [31: 0] read_data_global; - wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS); - novena_regs novena_regs_inst - ( - .clk(sys_clk), - .rst(sys_rst), - - .cs(enable_global & (sys_eim_rd | sys_eim_wr)), + ( + input wire sys_clk, + input wire sys_rst, + input wire sys_ena, + + input wire [13 : 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data + ); + + + /* In this memory segment (HASHES) we have 14 address bits. Every core has + * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here. + * + * Core #0 is not an actual HASH core, but a set of board-level (global) + * registers, that can be used to get information about hardware (board + * type, bitstream version and so on). + * + * So far we have three cores: SHA-1, SHA-256 and SHA-512. + */ + + /********************************************************* + * To add new HASH core named XXX follow the steps below * + ********************************************************* + * + * 1. Add corresponding `define under "List of Available Cores", this will + * allow users to exclude your core from implementation to save some + * slices in case they don't need it. + * + * `define USE_CORE_XXX + * + * + * 2. Choose address of your new core and add corresponding line under + * "Core Address Table". Core addresses can be in the range from 1 to 63 + * inclusively. Core address 0 is reserved for a page of global + * registers and must not be used. + * + * localparam CORE_ADDR_XXX = 6'dN; + * + * + * 3. Add instantiation of your new core after all existing cores + * surrounded by conditional synthesis directives. + * You also need a 32-bit output (read data) bus for your core and an + * enable flag. Note that sys_rst in an active-high sync reset signal. + * + * `ifdef USE_CORE_XXX + * wire [31: 0] read_data_xxx; + * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX); + * xxx xxx_inst + * ( + * .clk(sys_clk), + * .reset_n(~sys_rst), + * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), + * .we(sys_eim_wr), + * .address(addr_core_reg), + * .write_data(sys_write_data), + * .read_data(read_data_xxx), + * .error() + * ); + * `endif + * + * + * 4. Add previously created data bus to "Output (Read Data) Multiplexor" + * in the end of this file. + * + * `ifdef USE_CORE_XXX + * CORE_ADDR_XXX: + * sys_read_data_mux = read_data_xxx; + * `endif + * + */ + + + //---------------------------------------------------------------- + // Address Decoder + //---------------------------------------------------------------- + wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed + wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core + + + /* We can comment following lines to exclude cores from implementation + * in case we run out of slices. + */ + + //---------------------------------------------------------------- + // List of Available Cores + //---------------------------------------------------------------- + `define USE_CORE_SHA1 + `define USE_CORE_SHA256 + `define USE_CORE_SHA512 + + + //---------------------------------------------------------------- + // Core Address Table + //---------------------------------------------------------------- + localparam CORE_ADDR_GLOBAL_REGS = 6'd0; + localparam CORE_ADDR_SHA1 = 6'd1; + localparam CORE_ADDR_SHA256 = 6'd2; + localparam CORE_ADDR_SHA512 = 6'd3; + + + //---------------------------------------------------------------- + // Global Registers + //---------------------------------------------------------------- + wire [31: 0] read_data_global; + wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS); + novena_regs novena_regs_inst + ( + .clk(sys_clk), + .rst(sys_rst), + + .cs(enable_global & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_global) - ); - - - //---------------------------------------------------------------- - // SHA-1 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA1 - wire [31: 0] read_data_sha1; - wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1); - sha1 sha1_inst - ( - .clk(sys_clk), - .reset_n(~sys_rst), - - .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_global) + ); + + + //---------------------------------------------------------------- + // SHA-1 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA1 + wire [31: 0] read_data_sha1; + wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1); + sha1 sha1_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), - .address(addr_core_reg), - .write_data(sys_write_data), + .address(addr_core_reg), + .write_data(sys_write_data), .read_data(read_data_sha1) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-256 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA256 - wire [31: 0] read_data_sha256; - wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256); - sha256 sha256_inst - ( - .clk(sys_clk), - .reset_n(~sys_rst), - - .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), + ); + `endif + + + //---------------------------------------------------------------- + // SHA-256 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA256 + wire [31: 0] read_data_sha256; + wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256); + sha256 sha256_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), - .address(addr_core_reg), - .write_data(sys_write_data), + .address(addr_core_reg), + .write_data(sys_write_data), .read_data(read_data_sha256) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-512 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA512 - wire [31: 0] read_data_sha512; - wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512); - sha512 sha512_inst - ( - .clk(sys_clk), - .reset_n(~sys_rst), - - .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), + ); + `endif + + + //---------------------------------------------------------------- + // SHA-512 + //---------------------------------------------------------------- + `ifdef USE_CORE_SHA512 + wire [31: 0] read_data_sha512; + wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512); + sha512 sha512_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), - .address(addr_core_reg), - .write_data(sys_write_data), + .address(addr_core_reg), + .write_data(sys_write_data), .read_data(read_data_sha512) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - - always @* - // - case (addr_core_num) - // - CORE_ADDR_GLOBAL_REGS: sys_read_data_mux = read_data_global; - `ifdef USE_CORE_SHA1 CORE_ADDR_SHA1: sys_read_data_mux = read_data_sha1; `endif - `ifdef USE_CORE_SHA256 CORE_ADDR_SHA256: sys_read_data_mux = read_data_sha256; `endif - `ifdef USE_CORE_SHA512 CORE_ADDR_SHA512: sys_read_data_mux = read_data_sha512; `endif - // - default: sys_read_data_mux = {32{1'b0}}; - // - endcase - + ); + `endif + + + //---------------------------------------------------------------- + // Output (Read Data) Multiplexor + //---------------------------------------------------------------- + reg [31: 0] sys_read_data_mux; + assign sys_read_data = sys_read_data_mux; + + always @* + // + case (addr_core_num) + // + CORE_ADDR_GLOBAL_REGS: + sys_read_data_mux = read_data_global; + `ifdef USE_CORE_SHA1 + CORE_ADDR_SHA1: + sys_read_data_mux = read_data_sha1; + `endif + `ifdef USE_CORE_SHA256 + CORE_ADDR_SHA256: + sys_read_data_mux = read_data_sha256; + `endif + `ifdef USE_CORE_SHA512 + CORE_ADDR_SHA512: + sys_read_data_mux = read_data_sha512; + `endif + // + default: + sys_read_data_mux = {32{1'b0}}; + // + endcase endmodule -- cgit v1.2.3