From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Sat, 31 Jan 2015 09:03:06 +0100
Subject: Adding all main hw source files and constraints.

---
 .../clkmgr_dcm/simulation/timing/simulate_vcs.sh   | 72 ++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh

(limited to 'rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh')

diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
new file mode 100644
index 0000000..26a8c27
--- /dev/null
+++ b/rtl/src/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
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+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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+# CRITICAL APPLICATIONS
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+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+  vlogan -sverilog \
+           clkmgr_dcm_tb.v \
+           ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+        +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
-- 
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