From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 31 Jan 2015 09:03:06 +0100 Subject: Adding all main hw source files and constraints. --- .../simulation/functional/simulate_isim.bat | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat (limited to 'rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat') diff --git a/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat new file mode 100644 index 0000000..80904cb --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\clkmgr_dcm.v +vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v +vlogcomp -work work ..\clkmgr_dcm_tb.v + +REM compile the project +fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe + +REM run the simulation script +.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl -- cgit v1.2.3