From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 31 Jan 2015 09:03:06 +0100 Subject: Adding all main hw source files and constraints. --- rtl/src/ipcore/clkmgr_dcm.xdc | 67 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 rtl/src/ipcore/clkmgr_dcm.xdc (limited to 'rtl/src/ipcore/clkmgr_dcm.xdc') diff --git a/rtl/src/ipcore/clkmgr_dcm.xdc b/rtl/src/ipcore/clkmgr_dcm.xdc new file mode 100644 index 0000000..9ecc102 --- /dev/null +++ b/rtl/src/ipcore/clkmgr_dcm.xdc @@ -0,0 +1,67 @@ +# file: clkmgr_dcm.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.2 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- -- cgit v1.2.3