From 5150947e0bfc393b03e49bcb37e1168eb02f5b67 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sun, 1 Feb 2015 09:03:37 +0100 Subject: Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files. --- rtl/src/ipcore/clkmgr_dcm.v | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'rtl/src/ipcore/clkmgr_dcm.v') diff --git a/rtl/src/ipcore/clkmgr_dcm.v b/rtl/src/ipcore/clkmgr_dcm.v index b719b86..71477a8 100644 --- a/rtl/src/ipcore/clkmgr_dcm.v +++ b/rtl/src/ipcore/clkmgr_dcm.v @@ -55,7 +55,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase" // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" //---------------------------------------------------------------------------- -// CLK_OUT1____80.000______0.000______50.0______450.000____150.000 +// CLK_OUT1____50.000______0.000______50.0______200.000____150.000 // //---------------------------------------------------------------------------- // "Input Clock Freq (MHz) Input Jitter (UI)" @@ -92,12 +92,11 @@ module clkmgr_dcm wire [7:0] status_int; wire clkfb; wire clk0; - wire clkfx; DCM_SP #(.CLKDV_DIVIDE (2.000), - .CLKFX_DIVIDE (5), - .CLKFX_MULTIPLY (8), + .CLKFX_DIVIDE (1), + .CLKFX_MULTIPLY (4), .CLKIN_DIVIDE_BY_2 ("FALSE"), .CLKIN_PERIOD (20.0), .CLKOUT_PHASE_SHIFT ("NONE"), @@ -116,7 +115,7 @@ module clkmgr_dcm .CLK270 (), .CLK2X (), .CLK2X180 (), - .CLKFX (clkfx), + .CLKFX (), .CLKFX180 (), .CLKDV (), // Ports for dynamic phase shift @@ -133,17 +132,15 @@ module clkmgr_dcm .DSSEN (1'b0)); assign INPUT_CLK_STOPPED = status_int[1]; - assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2:1] == 2'b 0 ) ); + assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) ); // Output buffering //----------------------------------- - BUFG clkf_buf - (.O (clkfb), - .I (clk0)); + assign clkfb = CLK_OUT1; BUFG clkout1_buf (.O (CLK_OUT1), - .I (clkfx)); + .I (clk0)); -- cgit v1.2.3